Datasheet AD9059 (Analog Devices) - 10

AD9059 +VDD +V +V +V D D 3V TO 5V D 3k
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800
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500
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ENCODE VREF D0–D7 AIN VREF PWRDN 2.5k 2.5V
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DIGITAL INPUTS VOLTAGE REFERENCE DIGITAL OUTPUTS ANALOG INPUTS
Figure 6. Equivalent Circuits
Evaluation Board
Analog input signals to the board should be 1 V p-p into 50 Ω The AD9059/PCB evaluation board provides an easy-to-use for full-scale ADC drive. For ac-coupled operation, connect E7 analog/digital interface for the dual 8-bit, 60 MSPS ADC. The to E8 (analog input A to C12 feedthrough capacitor), E13 to board includes typical hardware configurations for a variety of high E15 (C12 to R15 termination resistor for Channel A), E4 to E6 speed digitization evaluations. On-board components include the (analog input B to C11 feedthrough capacitor), and E10 to E12 AD9059 (in the 28-lead SSOP package), optional analog input (C11 to R14 termination resistor for Channel B) using the buffer amplifiers, digital output latches, board timing drivers, and board jumper connectors. configurable jumpers for ac coupling, dc coupling, and power- The on-board reference voltage may be used to drive the ADC or down function testing. The board is configured at shipment for an external reference may be applied. The standard configuration dc coupling using the AD9059’s internal reference. employs the internal voltage reference without any external For dc-coupled analog input applications, amplifiers U3 and U4 connection requirements. An external voltage reference may be are configured to operate as unity gain inverters with adjustable applied at board connector input REF to overdrive the limited offset for the analog input signals. For full-scale ADC drive, current output of the AD9059’s internal voltage reference. The each analog input signal should be 1 V p-p into 50 Ω referenced external voltage reference should be 2.5 V typical. to ground. Each amplifier offsets its analog signal by +VREF The power-down function of the AD9059 can be exercised (2.5 V typical) to center the voltage for proper ADC input drive. through a board jumper connection. Connect E2 to E1 (5 V to For dc-coupled operation, connect E7 to E9 (analog input A to PWRDN) for power-down mode operation. For normal operation, R11), E14 to E13 (amplifier output to analog input A of connect E3 to E1 (ground to PWRDN). AD9059), E4 to E5 (analog input B to R10), and E11 to E10 The encode signal source should be TTL/CMOS compatible (amplifier output to analog input B of AD9059) using the board and capable of driving a 50 Ω termination. The digital outputs jumper connectors. of the AD9059 are buffered through latches on the evaluation For ac-coupled analog input applications, amplifiers U3 and U4 board (U5 and U6) and are available for the user at connector are removed from the analog signal paths. The analog signals Pins 30–37 and Pins 22–29. Latch timing is derived from the are coupled through Capacitors C11 and C12, each terminated ADC ENCODE clock and a digital clocking signal is provided to the VREF voltage through separate 1 kΩ resistors (providing for the board user at connector Pins 2 and 21. bias current for the AD9059 analog inputs, AINA and AINB). REV. A –9– Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION SPECIFICATIONS EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics THEORY OF OPERATION USING THE AD9059 Analog Inputs Voltage Reference Digital Logic (5 V/3 V Systems) Timing Power Dissipation Applications Evaluation Board OUTLINE DIMENSIONS Revision History