Datasheet AD7720 (Analog Devices) - 7

AD7720 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function
1 REF2 Reference Input/Output. REF2 connects to the output of an internal buffer amplifier used to drive the sigma-delta modulator. When REF2 is used as an input, REF1 must be con- nected to AGND. 2, 14, 18, 20, 24, 26 AGND Ground reference point for analog circuitry. 3, 13 NC No Connect. 4 STBY Standby, Logic Input. When STBY is high, the device is placed in a low power mode. When STBY is low, the device is powered up. 5 DVAL Data Valid Logic Output. A logic high on DVAL indicates that the data bit stream from the AD7720 is an accurate digital representation of the analog voltage at the input to the sigma-delta modulator. The DVAL pin is set low for 20 MCLK cycles if the analog input is overranged. 6, 15 DGND Ground reference for the digital circuitry. 7 GC Digital Control Input. When GC is high, the gain error of the modulator can be calibrated. 8 BIP Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A logic high selects bipolar mode. 9 MZERO Digital Control Input. When MZERO is high, the modulator inputs are internally grounded, i.e., tied to AGND in unipolar mode and REF2 in bipolar mode. MZERO allows on-chip offsets to be calibrated out. MZERO is low for normal operation. 10 DATA Modulator Bit Stream. The digital bit stream from the sigma-delta modulator is output at DATA. 11 SCLK Serial Clock, Logic Output. The bit stream from the modulator is valid on the rising edge of SCLK. 12 RESETO Reset Logic Output. The signal applied to the RESET pin is made available as an output at RESETO. 16 XTAL1/MCLK CMOS Logic Clock Input. The XTAL1/MCLK pin interfaces the device’s internal oscillator circuit to an external crystal or an external clock. A parallel resonant, fundamental-frequency, microprocessor-grade crystal and a 1 MΩ resistor should be connected between the MCLK and XTAL pins with two capacitors connected from each pin to ground. Alternatively, the XTAL1/MCLK pin can be driven with an external CMOS-compatible clock. The part is specified with a 12.5 MHz master clock. 17 XTAL2 Oscillator Output. The XTAL2 pin connects the internal oscillator output to an external crystal. If an external clock is used, XTAL2 should be left unconnected. 19 DVDD Digital Supply Voltage, +5 V ± 5%. 21, 23 VIN(–), VIN(+) Analog Input. In unipolar operation, the analog input range on VIN(+) is VIN(–) to (VIN(–) + VREF); for bipolar operation, the analog input range on VIN+ is (VIN(–) ± VREF/2). The absolute analog input range must lie between 0 and AVDD. The analog input is con- tinuously sampled and processed by the analog modulator. 25, 28 AVDD Analog Positive Supply Voltage, +5 V ± 5%. 22 RESET Reset Logic Input. RESET is an asynchronous input. When RESET is taken high, the sigma-delta modulator is reset by shorting the integrator capacitors in the modulator. DVAL goes low for 20 MCLK cycles while the modulator is being reset. 27 REF1 Reference Input/Output. REF1 connects via a 3 kΩ resistor to the output of the internal 2.5 V reference, and to the input of a buffer amplifier that drives the sigma-delta modulator. This pin can also be overdriven with an external 2.5 V reference. –6– REV. 0