Datasheet AD7731 (Analog Devices) - 5

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AD7731
NOTES 1 Temperature Range: –40°C to +85°C. 2 Sample tested during initial release. 3 No missing codes performance with CHP = 0 and SKIP = 1 is 22 bits. 4 The offset (or zero) numbers with CHP = 0 can be up to 1 mV precalibration. Internal zero-scale calibration reduces this to 2 µV typical. Offset numbers with CHP = 1 are typically 3 µV precalibration. Internal zero-scale calibration reduces this by about 1 µV. System zero-scale calibration reduces offset numbers with CHP = 0 and CHP = 1 to the order of the noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on all input ranges except the 20 mV and 40 mV input range reduces the gain error to less than 100 ppm. When operating on the 20 mV or 40 mV range, an internal full-scale calibration should be performed on the 80 mV input range with a resulting gain error of less than 250 ppm. System full-scale calibration reduces the gain error on all input ranges to the order of the noise. Positive and Negative Full-Scale Errors can be calculated from the offset and gain errors. 5 These numbers are generated during life testing of the part. 6 Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology. 7 Recalibration at any temperature will remove these errors. 8 Full-scale drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges. 9 Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points use to calculate the gain error are positive full-scale and negative full-scale. See Terminology. 10 Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed. 11 Power Supply Rejection and Common-Mode Rejection are given here for the upper and lower input voltage ranges. The rejection can be approximated to varying linearly (in dBs) between these values for the other input ranges. 12 The analog input voltage range on the AIN(+) inputs is given here with respect to the voltage on the respective AIN(–) input. 13 The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed. 14 The common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed. 15 These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load. 16 VDD refers to DVDD for all logic outputs expect D0 and D1 where it refers to AVDD. In other words, the output logic high for these two outputs is determined by AVDD. 17 See Burnout Current section. 18 After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s. 19 These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. Specifications subject to change without notice.
(AV TIMING CHARACTERISTICS1, 2 DD = +4.75 V to +5.25 V; DVDD = +2.7 V to +5.25 V; AGND = DGND = 0 V; fCLK IN = 4.9152 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted) Limit at TMIN, TMAX Parameter (B Version) Units Conditions/Comments
Master Clock Range 1 MHz min For Specified Performance 5 MHz max t1 50 ns min SYNC Pulse Width t2 50 ns min RESET Pulse Width
Read Operation
t3 0 ns min RDY to CS Setup Time t4 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t 4 5 0 ns min SCLK Active Edge to Data Valid Delay3 60 ns max DVDD = +4.75 V to +5.25 V 80 ns max DVDD = +2.7 V to +3.3 V t 4, 5 5A 0 ns min CS Falling Edge to Data Valid Delay3 60 ns max DVDD = +4.75 V to +5.25 V 80 ns max DVDD = +2.7 V to +3.3 V t6 100 ns min SCLK High Pulse Width t7 100 ns min SCLK Low Pulse Width t8 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time3 t 6 9 10 ns min Bus Relinquish Time after SCLK Inactive Edge3 80 ns max t10 100 ns max SCLK Active Edge to RDY High3, 7
Write Operation
t11 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t12 30 ns min Data Valid to SCLK Edge Setup Time t13 25 ns min Data Valid to SCLK Edge Hold Time t14 100 ns min SCLK High Pulse Width t15 100 ns min SCLK Low Pulse Width t16 0 ns min CS Rising Edge to SCLK Edge Hold Time NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figures 15 and 16. 3 SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0. 4 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 5 This specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is required primarily for interfacing to DSP machines. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo- lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. –4– REV. 0 REV. A Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM AD7731-SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Ordering Guide ESD Caution PIN CONFIGURATION Pin Function Descriptions TERMINOLOGY OUTPUT NOISE AND RESOLUTION SPECIFICATION Output Noise (CHP = 0, SKIP= 1) Output Noise (CHP = 1, SKIP = 0) ON-CHIP REGISTERS Communications Register (RS2-RS0 = 0, 0, 0) Status Register (RS2-RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex Data Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex Mode Register (RS2-RS0 = 0, 1, 0); Power-On/Reset Status: 0174 Hex Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 2002 Hex Offset Calibration Register (RS2-RS0 = 1, 0, 1) Gain Calibration Register (RS2-RS0 = 1, 1, 0) Test Register (RS2-RS0 = 1, 1, 1); Power On/Reset Status: 000000 Hex READING FROM AND WRITING TO THE ON-CHIP REGISTERS CALIBRATION OPERATION SUMMARY CIRCUIT DESCRIPTION ANALOG INPUT Analog Input Channels Buffered Inputs Analog Input Ranges Programmable Gain Amplifier Bipolar/Unipolar Inputs Burnout Currents REFERENCE INPUT Reference Detect SIGMA-DELTA MODULATOR DIGITAL FILTERING Filter Architecture First State Filter/SKIP Mode Enabled (SKIP =1) Nonchop Mode (SKIP =1, CHP = 0) Chop Mode (SKIP = 1, CHP =1) Second Stage Filter Normal FIR Operation (SKIP = 0) Chop Mode (SKIP = 0, CHP =1) Nonchop Mode (SKIP = 1, CHP = 0) FASTStep Mode (SKIP = 0, FAST = 1) CALIBRATION Internal Zero-Scale Calibration Internal Full-Scale Calibration System Zero-Scale Calibration System Full-Scale Calibration Span and Offset Limits Power-Up and Calibration Drift Considerations USING THE AD7731 Clocking and Oscillator Circuit System Synchronization Single-Shot Conversions Reset Input Standby Mode Digital Outputs POWER SUPPLIES Grounding and Layout Evaluting the AD7731 Performance SERIAL INTERFACE Write Operation Read Operation CONFIGURING THE AD7731 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7731 to 68HC11 Interface AD7731 to 8051 Interface AD7731 to ADSP-2103/ADSP-2105 Interface APPLICATIONS Data Acquisition Programmable Logic Controllers Pressure Measurement Temperature Measurement Bipolar Input Signals PAGE INDEX TABLE INDEX OUTLINE DIMENSIONS