AD6640085AIN = 19.5MHzENCODE = 65MSPS AIN = 15.0MHz, 16.0MHz20NO DITHERWORST SPUR8040756070SNR8065100SNR, WORST CASE SPURIOUS – dB, dBcPOWER RELATIVE TO ADC FULL SCALE – dB12060dc6.513.019.526.032.5dc8162432404856647280FREQUENCY – MHzSAMPLE RATE – MSPS TPC 7. Two Tones at 15.0 MHz and 16.0 MHz TPC 10. SNR, Worst Spurious vs. ENCODE 10090ENCODE = 65MSPS9085dBFSAIN = 2.2MHz8080WORST SPUR757070ENCODE = 65MSPSSNR60AIN = 31.0MHz655060SFDR = 80dB4055dBcREFERENCE LINE50304520401035WORST CASE SPURIOUS – dBc and dBFS0SNR, WORST FULL-SCALE SPURIOUS – dB, dBc 30–80–70–60–50–40–30–20–1002530354045505560657075ANALOG INPUT POWER LEVEL – dBFSENCODE DUTY CYCLE – % TPC 8. Single Tone SFDR TPC 11. SNR, Worst Spurious vs. Duty Cycle 100909085ENCODE = 65MSPS2.2MHzWORST SPURdBFS808069MHz7570dBc70ENCODE = 65MSPS60F1 = 15.0MHz652.2MHzSNR50F2 = 16.0MHz6069MHzSFDR = 80dB4055REFERENCE LINE50304520401035WORST CASE SPURIOUS – dBc and dBFS0SNR, WORST FULL-SCALE SPURIOUS – dB, dBc 30–80–70–60–50–40–30–20–100–15–12–9–6–303691215INPUT POWER LEVEL (F1 = F2) – dBFSENCODE POWER – dBm TPC 9. Two Tone SFDR TPC 12. SNR, Worst Spurious vs. ENCODE Power REV. A –9– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal) Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Power Supply Rejection Ratio Signal-to-Noise-and-Distortion (SINAD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR Worst Harmonic Equivalent Circuits Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD6640 Encoding the AD6640 Driving the Analog Input Power Supplies Output Loading Layout Information Evaluation Boards DIGITAL WIDEBAND RECEIVERS Introduction System Description System Requirements Noise Floor and SNR Processing Gain Overcoming Static Nonlinearities with Dither Receiver Example IF Sampling Using the AD6640 as a Mix-Down Stage RECEIVE CHAIN FOR A PHASED-ARRAY CELLULAR BASE STATION OUTLINE DIMENSIONS Revision History