Datasheet AD7707 (Analog Devices) - 2

AD7707* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS
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Technical Articles
• Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter
DOCUMENTATION
• MS-2210: Designing Power Supplies for High Speed ADC
Application Notes
• Part 1: Circuit Suggestions Using Features and • AN-202: An IC Amplifier User’s Guide to Decoupling, Functionality of New Sigma-Delta ADCs Grounding, and Making Things Go Right for a Change • Part 2: Circuit Suggestions Using Features and • AN-283: Sigma-Delta ADCs and DACs Functionality of New Sigma-Delta ADCs • AN-311: How to Reliably Protect CMOS Circuits Against Power Supply Overvoltaging
DESIGN RESOURCES
• AN-388: Using Sigma-Delta Converters-Part 1 • AD7707 Material Declaration • AN-389: Using Sigma-Delta Converters-Part 2 • PCN-PDN Information • AN-397: Electrically Induced Damage to Standard Linear • Quality And Reliability Integrated Circuits: • Symbols and Footprints • AN-607: Selecting a Low Bandwidth (<15 kSPS) Sigma- Delta ADC
DISCUSSIONS
• AN-615: Peak-to-Peak Resolution Versus Effective View all AD7707 EngineerZone Discussions. Resolution
Data Sheet SAMPLE AND BUY
• AD7707: 3 V/5 V, ±10 V Input Range, 1 mW 3-Channel 16- Bit, Sigma-Delta ADC Data Sheet Visit the product page to see pricing options.
TOOLS AND SIMULATIONS TECHNICAL SUPPORT
• Sigma-Delta ADC Tutorial Submit a technical question or find your regional support number.
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Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION) OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (3 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (3 V OPERATION) ON-CHIP REGISTERS COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01 Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 0x05 Data Register (RS2, RS1, RS0 = 0, 1, 1) Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 0x00 Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 0x1F4000 Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 0x5761AB CALIBRATION SEQUENCES CIRCUIT DESCRIPTION ANALOG INPUT ANALOG INPUT RANGES INPUT SAMPLE RATE BIPOLAR/UNIPOLAR INPUTS REFERENCE INPUT DIGITAL FILTERING FILTER CHARACTERISTICS POSTFILTERING ANALOG FILTERING CALIBRATION SELF-CALIBRATION SYSTEM CALIBRATION SPAN AND OFFSET LIMITS ON THE LOW LEVEL INPUT CHANNELS, AIN1 AND AIN2 SPAN AND OFFSET LIMITS ON THE HIGH LEVEL INPUT CHANNEL AIN3 POWER-UP AND CALIBRATION USING THE AD7707 CLOCKING AND OSCILLATOR CIRCUIT SYSTEM SYNCHRONIZATION RESET INPUT STANDBY MODE ACCURACY DRIFT CONSIDERATIONS POWER SUPPLIES SUPPLY CURRENT GROUNDING AND LAYOUT DIGITAL INTERFACE CONFIGURING THE AD7707 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7707 TO 68HC11 INTERFACE AD7707 TO 8XC51 INTERFACE CODE FOR SETTING UP THE AD7707 C CODE FOR INTERFACING AD7707 TO 68HC11 APPLICATIONS INFORMATION DATA ACQUISITION SMART VALVE/ACTUATOR CONTROL PRESSURE MEASUREMENT THERMOCOUPLE MEASUREMENT RTD MEASUREMENT CHART RECORDERS ACCOMMODATING VARIOUS HIGH LEVEL INPUT RANGES TYPICAL INPUT CURRENTS OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL, AIN3 5 V OPERATION 3 V OPERATION OUTLINE DIMENSIONS ORDERING GUIDE