Datasheet AD7654 (Analog Devices) - 5

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AD7654 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL OUTPUTS Data Format6 Pipeline Delay7 VOL ISINK = 1.6 mA 0.4 V VOH ISOURCE = −500 μA OVDD − 0.2 V POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.258 V Operating Current9 500 kSPS throughput AVDD 15.5 mA DVDD 8.5 mA OVDD 100 μA Power Dissipation 500 kSPS throughput9 120 135 mW 10 kSPS throughput10 2.6 mW 444 kSPS throughput10 114 125 mW TEMPERATURE RANGE11 Specified Performance TMIN to TMAX −40 +85 °C 1 See the Analog Inputs section. 2 Linearity is tested using endpoints, not best fit. 3 LSB means least significant bit. Within the 0 V to 5 V input range, one LSB is 76.294 μV. 4 See the Terminology section. These specifications do not include the error contribution from the external reference. 5 All specifications in dB are referred to as full-scale input, FS; tested with an input signal at 0.5 dB below full scale unless otherwise specified. 6 Parallel or serial 16-bit. 7 Conversion results are available immediately after completed conversion. 8 The maximum should be the minimum of 5.25 V and DVDD + 0.3 V. 9 In normal mode; tested in parallel reading mode. 10 In impulse mode; tested in parallel reading mode. 11 Consult sales for extended temperature range. Rev. D | Page 4 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION CIRCUIT INFORMATION MODES OF OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS INPUT CHANNEL MULTIPLEXER DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT POWER SUPPLY POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) Channel A//B Output SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Convert External Clock Data Read Previous During Convert MICROPROCESSOR INTERFACING SPI INTERFACE (ADSP-2191M) APPLICATION HINTS LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE