Datasheet AD9236 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 80 MSPS, 3 V A/D Converter |
| Seiten / Seite | 37 / 7 — AD9236. Data Sheet. SWITCHING SPECIFICATIONS. Table 4. … |
| Revision | C |
| Dateiformat / Größe | PDF / 1.3 Mb |
| Dokumentensprache | Englisch |
AD9236. Data Sheet. SWITCHING SPECIFICATIONS. Table 4. AD9236BRU/AD9236BCP. Parameter Temp. Test. Level. Min Typ Ma. Unit. N+1. N+2. N+8. N–1. N+3
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AD9236 Data Sheet SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4. AD9236BRU/AD9236BCP Parameter Temp Test Level Min Typ Ma Unit x
CLOCK INPUT PARAMETERS Maximum Conversion Rate Full VI 80 MSPS Minimum Conversion Rate Full V 1 MSPS CLK Period Full V 12.5 ns CLK Pulse Width High1 Full V 4.0 ns CLK Pulse Width Low1 Full V 4.0 ns DATA OUTPUT PARAMETERS Output Propagation Delay (tPD)2 Full V 3.5 ns Pipeline Delay (Latency) Full V 7 Cycles Aperture Delay (tA) Full V 1.0 ns Aperture Uncertainty (Jitter, tJ) Full V 0.3 ps rms Wake-Up Time3 Full V 7 ms OUT OF RANGE RECOVERY TIME Full V 2 Cycles 1 With duty cycle stabilizer (DCS) enabled. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
N+1 N N+2 N+8 N–1 N+3 t ANALOG A INPUT N+7 N+4 N+5 N+6 CLK DATA N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N OUT tPD = 6.0ns MAX 2.0ns MIN
03066-0-002 Figure 2. Timing Diagram
Table 5. Explanation of Test Levels Test Level Definitions
I 100% production tested. II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. Rev. C | Page 6 of 36 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History DC Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Terminology Pin Configurations and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input and Reference Overview Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Timing Voltage Reference Internal Reference Connection External Reference Operation Operational Mode Selection Evaluation Board TSSOP Evaluation Board LFCSP Evaluation Board Outline Dimensions Ordering Guide
AD9236 Data Sheet SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4. AD9236BRU/AD9236BCP Parameter Temp Test Level Min Typ Ma Unit x
CLOCK INPUT PARAMETERS Maximum Conversion Rate Full VI 80 MSPS Minimum Conversion Rate Full V 1 MSPS CLK Period Full V 12.5 ns CLK Pulse Width High1 Full V 4.0 ns CLK Pulse Width Low1 Full V 4.0 ns DATA OUTPUT PARAMETERS Output Propagation Delay (tPD)2 Full V 3.5 ns Pipeline Delay (Latency) Full V 7 Cycles Aperture Delay (tA) Full V 1.0 ns Aperture Uncertainty (Jitter, tJ) Full V 0.3 ps rms Wake-Up Time3 Full V 7 ms OUT OF RANGE RECOVERY TIME Full V 2 Cycles 1 With duty cycle stabilizer (DCS) enabled. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
N+1 N N+2 N+8 N–1 N+3 t ANALOG A INPUT N+7 N+4 N+5 N+6 CLK DATA N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N OUT tPD = 6.0ns MAX 2.0ns MIN
03066-0-002 Figure 2. Timing Diagram
Table 5. Explanation of Test Levels Test Level Definitions
I 100% production tested. II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. Rev. C | Page 6 of 36 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History DC Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Terminology Pin Configurations and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input and Reference Overview Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Timing Voltage Reference Internal Reference Connection External Reference Operation Operational Mode Selection Evaluation Board TSSOP Evaluation Board LFCSP Evaluation Board Outline Dimensions Ordering Guide