Datasheet AD7653 (Analog Devices) - 6

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Data Sheet AD7653 TIMING SPECIFICATIONS Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter Symbol Min Typ Max Unit
Refer to Figure 26 and Figure 27 Convert Pulse Width t1 10 ns Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)1 t2 1/1.25/1.5 μs CNVST LOW to BUSY HIGH Delay t3 35 ns BUSY HIGH All Modes Except Master Serial Read after Convert (Warp Mode/Normal Mode/Impulse Mode) t4 0.75/1/1.25 μs Aperture Delay t5 2 ns End of Conversion to BUSY LOW Delay t6 10 ns Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t7 0.75/1/1.25 μs Acquisition Time t8 250 ns RESET Pulse Width t9 10 ns Refer to Figure 28, Figure 29, and Figure 30 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) t10 0.75/1/1.25 μs DATA Valid to BUSY LOW Delay t11 12 ns Bus Access Request to DATA Valid t12 45 ns Bus Relinquish Time t13 5 15 ns Refer to Figure 32 and Figure 33 (Master Serial Interface Modes)2 CS LOW to SYNC Valid Delay t14 10 ns CS LOW to Internal SCLK Valid Delay2 t15 10 ns CS LOW to SDOUT Delay t16 10 ns CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) t17 25/275/525 ns SYNC Asserted to SCLK First Edge Delay t18 3 ns Internal SCLK Period3 t19 25 40 ns Internal SCLK HIGH3 t20 12 ns Internal SCLK LOW3 t21 7 ns SDOUT Valid Setup Time3 t22 4 ns SDOUT Valid Hold Time3 t23 2 ns SCLK Last Edge to SYNC Delay3 t24 3 ns CS HIGH to SYNC HI-Z t25 10 ns CS HIGH to Internal SCLK HI-Z t26 10 ns CS HIGH to SDOUT HI-Z t27 10 ns BUSY HIGH in Master Serial Read after Convert3 (Warp Mode/Normal Mode/Impulse Mode) t28 See Table 4 CNVST LOW to SYNC Asserted Delay (Warp Mode/Normal Mode/Impulse Mode) t29 0.75/1/1.25 μs SYNC Deasserted to BUSY LOW Delay t30 25 ns Refer to Figure 34 and Figure 35 (Slave Serial Interface Modes) 2 External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 3 18 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns 1 In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 3 In Serial Master Read during Convert Mode. See Table 4 for Serial Master Read after Convert mode. Rev. B | Page 5 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Hightlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Definitions of Specifications Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Overvoltage Recovery Reference Voltage Temperature Coefficient Typical Performance Characteristics Circuit Information Converter Operation Modes of Operation Transfer Functions Typical Connection Diagram Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply Power Dissipation vs. Throughput Conversion Control Digital Interface Parallel Interface Serial Interface Master Serial Interface Internal Clock Slave Serial Interface External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Conversion Microprocessor Interfacing SPI Interface (ADSP-2191M) Application Hints Bipolar and Wider Input Ranges Layout Outline Dimensions Ordering Guide