Datasheet AD7653 (Analog Devices) - 10

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Data Sheet AD7653 Pin No. Mnemonic Type1 Description
13 D4 or EXT/INT DI/O When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choos- ing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D5 or DI/O When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus. INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D6 or DI/O When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus. INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave modes. 16 D7 or DI/O When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus. RDC/SDIN When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground. 21 D8 or DO When SER/PAR is LOW, this output is used as Bit 8 of the parallel port data output bus. SDOUT When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchro- nized to SCLK. Conversion results are stored in an on-chip register. The AD7653 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode when EXT/INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. 22 D9 or DI/O When SER/PAR is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus. SCLK When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D10 or DO When SER/PAR is LOW, this output is used as Bit 10 of the parallel port data output bus. SYNC When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while the SDOUT output is valid. 24 D11 or DO When SER/PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. When RDERROR SER/PAR and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. 25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the state of SER/PAR. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. 30 DGND P Must Be Tied to Digital Ground. 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. Rev. B | Page 9 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Hightlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Definitions of Specifications Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Overvoltage Recovery Reference Voltage Temperature Coefficient Typical Performance Characteristics Circuit Information Converter Operation Modes of Operation Transfer Functions Typical Connection Diagram Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply Power Dissipation vs. Throughput Conversion Control Digital Interface Parallel Interface Serial Interface Master Serial Interface Internal Clock Slave Serial Interface External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Conversion Microprocessor Interfacing SPI Interface (ADSP-2191M) Application Hints Bipolar and Wider Input Ranges Layout Outline Dimensions Ordering Guide