Datasheet AD7452 (Analog Devices) - 10

Data Sheet AD7452 Negative Gain Error Power Supply Rejection Ratio (PSRR)
This is the deviation of the first code transition (100. .000 to The ratio of the power in the ADC output at ful -scale fre- 100.. 001) from the ideal VIN+ – VIN– (that is, –VREF + 1 LSB), quency, f, to the power of a 100 mV p-p sine wave applied to the after the zero code error has been adjusted out. ADC VDD supply of frequency fS. The frequency of this input varies from 1 kHz to 1 MHz.
Track-and-Hold Acquisition Time
The minimum time required for the track-and-hold amplifier PSRR(dB) = 10log(Pf/PfS) to remain in track mode for its output to reach and settle to Pf is the power at frequency f in the ADC output; Pfs is the within 0.5 LSB of the applied input signal. power at frequency fS in the ADC output. Rev. C | Page 9 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT Analog Input Structure DRIVING DIFFERENTIAL INPUTS Differential Amplifier Op Amp Pair RF Transformer DIGITAL INPUTS REFERENCE Example 1 Example 2 SINGLE-ENDED OPERATION SERIAL INTERFACE Timing Example MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER vs. THROUGHPUT RATE APPLICATION HINTS Grounding and Layout EVALUATING THE AD7452’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE