Datasheet AD9461 (Analog Devices)

16-Bit, 130 MSPS IF Sampling ADC AD9461 FEATURES FUNCTIONAL BLOCK DIAGRAM 130 MSPS guaranteed sampling rate AGND AVDD1 AVDD2 DRGND DRVDD 78.7 dBFS SNR/90 dBc SFDR with 10 MHz input DFS (3.4 V p-p input, 130 MSPS) AD9461 DCS MODE 77.7 dBFS SNR with 170.3 MHz input BUFFER OUTPUT MODE 16 (4.0 V p-p input, 130 MSPS) VIN+ 2 T/H PIPELINE CMOS OR VIN– ADC OR 77.0 dBFS SNR/84 dBc SFDR with 170 MHz input LVDS 32 (3.4 V p-p input, 130 MSPS) OUTPUT D15 TO D0 STAGING 76.3 dBFS SNR/86 dBc SFDR with 225 MHz input 2 CLK+ CLOCK (3.4 V p-p input, 125 MSPS) AND TIMING DCO CLK– MANAGEMENT REF 89 dBFS two-tone SFDR with 169 MHz and 170 MHz (130 MSPS)
001
60 fsec rms jitter
1-
VREF SENSE REFT REFB
0601
Excellent linearity
Figure 1.
DNL = ±0.6 LSB typical INL = ±5.0 LSB typical 2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output clock available APPLICATIONS MRI receivers
Optional features allow users to implement various selectable
Multicarrier, multimode, cellular receivers
operating conditions, including input range, data format select,
Antenna array positioning
and output data mode.
Power amplifier linearization Broadband wireless
The AD9461 is available in a Pb-free, 100-lead, surface-mount,
Radar
plastic package (100-lead TQFP_EP) specified over the industrial
Infrared imaging
temperature range −40°C to +85°C.
Communications instrumentation PRODUCT HIGHLIGHTS GENERAL DESCRIPTION
1. True 16-bit linearity. The AD9461 is a 16-bit, monolithic, sampling, analog-to-digital 2. High performance: outstanding SNR performance for converter (ADC) with an on-chip track-and-hold circuit. It is baseband IFs in data acquisition, instrumentation, optimized for performance, small size, and ease of use. The magnetic resonance imaging, and radar receivers. AD9461 operates up to 130 MSPS, providing a superior signal- to-noise ratio (SNR) for instrumentation, medical imaging, and 3. Ease of use: on-chip reference and high input impedance radar receivers using baseband (<100 MHz) and IF frequencies. track-and-hold with adjustable analog input range and an output clock simplifies data capture. The ADC requires 3.3 V and 5.0 V power supplies and a low 4. Packaged in a Pb-free, 100-lead TQFP_EP. voltage differential input clock for full performance operation. No external reference or driver components are required for 5. Clock duty cycle stabilizer (DCS) maintains overall ADC many applications. Data outputs are CMOS or LVDS compatible performance over a wide range of clock pulse widths. (ANSI-644 compatible) and include the means to reduce the 6. Out-of-range (OR) outputs indicate when the signal is overall current needed for short trace distances. beyond the selected input range.
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer SFDR Enhancement EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE