Datasheet AD7829-1 (Analog Devices) - 8

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AD7829-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DB2 1 28 DB3 DB1 2 27 DB4 DB0 3 26 DB5 CONVST 4 25 DB6 CS 5 24 DB7 RD 6 AD7829-1 23 AGND DGND TOP VIEW 7 22 VDD (Not to Scale) EOC 8 21 VREF IN/OUT A2 9 20 VMID A1 10 19 VIN1 A0 11 18 VIN2 VIN8 12 17 VIN3 VIN7 13 16 VIN4
03 0 9-
VIN6 14 15 VIN5
17 06 Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
12 to 19 VIN8 to VIN1 Analog Input Channels. The AD7829-1 has eight analog input channels. The inputs have an input span of 2.5 V and 2 V, depending on the supply voltage (VDD). This span can be centered anywhere in the range AGND to VDD using the VMID pin. The default input range (VMID unconnected) is AGND to 2 V (VDD = 3 V ± 10%) or AGND to 2.5 V (VDD = 5 V ± 10%). See the Analog Input section of the data sheet for more information. 22 VDD Positive Supply Voltage, 3 V ± 10% and 5 V ± 10%. 23 AGND Analog Ground. Ground reference for track/hold, comparators, reference circuit, and multiplexer. 7 DGND Digital Ground. Ground reference for digital circuitry. 4 CONVST Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of this signal. The falling edge of this signal places the track/hold in hold mode. The track/hold goes into track mode again 120 ns after the start of a conversion. The state of the CONVST signal is checked at the end of a conversion. If it is logic low, the AD7829-1 powers down (see the Operating Modes section). 8 EOC Logic Output. The end of conversion signal indicates when a conversion has finished. The signal can be used to interrupt a microcontroller when a conversion has finished or latch data into a gate array (see the Parallel Interface section). 5 CS Logic Input Signal. The chip select signal is used to enable the parallel port of the AD7829. This is necessary if the ADC is sharing a common data bus with another device. 6 RD Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and drive data onto the data bus. The signal is internally gated with the CS signal. Both RD and CS must be logic low to enable the data bus. 9 to 11 A2 to A0 Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the RD signal goes low. 1 to 3, DB2 to DB0, Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when 24 to 28 DB7 to DB3 both RD and CS go active low. 21 VREF IN/OUT Analog Input and Output. An external reference can be connected to the AD7829-1 at this pin. The on-chip reference is also available at this pin. When using the internal reference, this pin can be left unconnected or, in some cases, it can be decoupled to AGND with a 0.1 μF capacitor. 20 VMID The VMID pin, if connected, is used to center the analog input span anywhere in the range of AGND to VDD (see the Analog Input section). Rev. 0 | Page 7 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY CIRCUIT INFORMATION CIRCUIT DESCRIPTION TYPICAL CONNECTION DIAGRAM ADC TRANSFER FUNCTION ANALOG INPUT POWER-UP TIMES POWER VS. THROUGHPUT OPERATING MODES PARALLEL INTERFACE MICROPROCESSOR INTERFACING AD7829-1 TO 8051 AD7829-1 TO PIC16C6x/PIC16C7x AD7829-1 TO ADSP-21xx INTERFACING MULTIPLEXER ADDRESS INPUTS OUTLINE DIMENSIONS ORDERING GUIDE