Datasheet AD7610 (Analog Devices) - 26
Hersteller | Analog Devices |
Beschreibung | 16-Bit, 250 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC |
Seiten / Seite | 33 / 26 — Data Sheet. AD7610. EXT/INT = 0. RDC/SDIN = 0. INVSCLK = INVSYNC = 0. CS, … |
Revision | A |
Dateiformat / Größe | PDF / 694 Kb |
Dokumentensprache | Englisch |
Data Sheet. AD7610. EXT/INT = 0. RDC/SDIN = 0. INVSCLK = INVSYNC = 0. CS, RD. CNVST. BUSY. t28. t30. t29. t25. SYNC. t14. t18 t19. t21. t26. SDCLK. t15. t27
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Textversion des Dokuments
Data Sheet AD7610 EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 CS, RD t3 CNVST BUSY t28 t30 t29 t25 SYNC t14 t18 t19 t t 20 t21 24 t26 SDCLK 1 2 3 14 15 16 t15 t27 SDOUT X D15 D14 D2 D1 D0
39
t
0
16 t23
5-
t22
39 06 Figure 39. Master Serial Data Timing for Reading (Read After Convert)
EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t1 CNVST t3 BUSY t17 t25 SYNC t14 t19 t20 t21 t24 t26 t15 SDCLK 1 2 3 14 15 16 t18 t27 SDOUT X D15 D14 D2 D1 D0
0 4
t
0
16 t23
5-
t22
39 06 Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. A | Page 25 of 32 Document Outline Features Functional Block Diagram Applications General Description Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Converter Operation Transfer Functions Typical Connection Diagram Analog Inputs Input Range Selection Input Structure Voltage Reference Input/Output Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V) (PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor Power Supplies Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down Conversion Control Interfaces Digital Interface RESET Parallel Interface Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) Serial Interface Data Interface Master Serial Interface Internal Clock (SER/ = High, EXT/ = Low) Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) Read During Convert (RDC = High) Slave Serial Interface External Clock (SER/ = High, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion Hardware Configuration Software Configuration Microprocessor Interfacing SPI Interface Application Information Layout Guidelines Evaluating Performance Outline Dimensions Ordering Guide