Datasheet AD7612 (Analog Devices) - 4

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Data Sheet AD7612 SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Conditions/Comments Min Typ Max Unit
RESOLUTION 16 Bits ANALOG INPUT Voltage Range, VIN VIN+ − VIN− = 0 V to 5 V −0.1 +5.1 V VIN+ − VIN− = 0V to 10 V −0.1 +10.1 V VIN+ − VIN− = ±5 V −5.1 +5.1 V VIN+ − VIN− = ±10 V −10.1 +10.1 V VIN− to AGND −0.1 +0.1 V Analog Input CMRR fIN = 100 kHz 75 dB Input Current VIN = ±5 V, ±10 V @ 750 kSPS 2201 μA Input Impedance See Analog Inputs section THROUGHPUT SPEED Complete Cycle In warp mode 1.33 μs Throughput Rate In warp mode 1 7502 kSPS Time Between Conversions In warp mode 1 ms Complete Cycle In normal mode 1.67 μs Throughput Rate In normal mode 0 600 kSPS Complete Cycle In impulse mode 2 μs Throughput Rate In impulse mode 0 500 kSPS DC ACCURACY Integral Linearity Error3 −1.5 ±0.75 +1.5 LSB4 No Missing Codes3 16 Bits Differential Linearity Error3 −1 +1.5 LSB Transition Noise 0.55 LSB Zero Error (Unipolar or Bipolar) −35 +35 LSB Zero Error Temperature Drift ±1 ppm/°C Bipolar Full-Scale Error −50 +50 LSB Unipolar Full-Scale Error −70 +70 LSB Full-Scale Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% 3 LSB AC ACCURACY Dynamic Range VIN = 0 V to 5 V, fIN = 2 kHz, −60 dB 92.5 93.5 dB5 VIN = 0 V to 10 V, ±5 V, fIN = 2 kHz, −60 dB 94 dB VIN = ±10 V, fIN = 2 kHz, −60 dB 94.5 dB Signal-to-Noise Ratio VIN = 0 V to 5 V, 0 V to 10 V, fIN = 2 kHz 92 93 dB VIN = ±5 V, ±10 V, fIN = 2 kHz 94 dB Signal-to-(Noise + Distortion) (SINAD) VIN = ±5 V, fIN = 2 kHz 92.5 dB VIN = 0 V to 10 V, ±5 V, fIN = 2 kHz 93 dB VIN = ±10 V, fIN = 2 kHz 93.5 dB Total Harmonic Distortion fIN = 2 kHz −107 dB Spurious-Free Dynamic Range fIN = 2 kHz 107 dB –3 dB Input Bandwidth VIN = 0 V to 5 V 45 MHz Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 500 ns INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 4.965 5.000 5.035 V Temperature Drift –40°C to +85°C ±3 ppm/°C Line Regulation AVDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time CREF = 22 μF 10 ms Rev. A | Page 3 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V) (PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface MASTER SERIAL INTERFACE Internal Clock (SER/ = high, EXT/ = Low) Read During Convert (RDC = High) Read During Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) SLAVE SERIAL INTERFACE External Clock (SER/ = High, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE