Datasheet AD7612 (Analog Devices)

16-Bit, 750 kSPS, Unipolar/Bipolar Programmable Input PulSAR® ADC Data Sheet AD7612 FEATURES FUNCTIONAL BLOCK DIAGRAM Multiple pins/software programmable input ranges: TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND 5 V, 10 V, ±5 V, ±10 V OVDD Pins or serial SPI®-compatible input ranges/mode selection AGND AD7612 REF OGND AVDD AMP Throughput SERIAL DATA PDREF REF PORT 750 kSPS (warp mode) PDBUF SERIAL 600 kSPS (normal mode) CONFIGURATION IN+ PORT 16 SWITCHED D[15:0] 500 kSPS (impulse mode) CAP DAC IN– SER/PAR INL: ±0.75 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR) BYTESWAP 16-bit resolution with no missing codes PARALLEL CLOCK OB/2C INTERFACE SNR: 92 minimum (5 V) @ 2 kHz, 94 dB typical (±10 V) @ 2 kHz CNVST BUSY PD THD: −107 dB typical CONTROL LOGIC AND CALIBRATION CIRCUITRY RD RESET i CMOS™ process technology CS 5 V internal reference: typical drift 3 ppm/°C; TEMP output
001
No pipeline delay (SAR architecture) WARP IMPULSE BIPOLAR TEN
06265-
Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface
Figure 1.
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection Power dissipation: 190 mW @ 750 kSPS 100 kSPS to 500 kSPS to 800 kSPS to >1000 Pb-free, 48-lead LQFP and LFCSP (7 mm × 7 mm) packages Type 250 kSPS 570 kSPS 1000 kSPS kSPS
Pseudo AD7651 AD7650 AD7653
APPLICATIONS
Differential AD7660 AD7652 AD7667
Process control
AD7661 AD7664 AD7666
Medical instruments
True Bipolar AD7663 AD7665 AD7612
High speed data acquisition
AD7671
Digital signal processing
True AD7675 AD7676 AD7677 AD7621
Instrumentation
Differential AD7622 AD7623
Spectrum analysis
18-Bit, True AD7678 AD7679 AD7674 AD7641
ATE
Differential AD7643
GENERAL DESCRIPTION
Multichannel/ AD7654 Simultaneous AD7655 The AD7612 is a 16-bit charge redistribution successive approximation register (SAR), architecture analog-to-digital
PRODUCT HIGHLIGHTS
converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS 1. Programmable input range and mode selection. high voltage process. The device is configured through hardware or Pins or serial port for selecting input range/mode select. via a dedicated write only serial configuration port for input 2. Fast throughput. range and operating mode. The AD7612 contains a high speed In warp mode, the AD7612 is 750 kSPS. 16-bit sampling ADC, an internal conversion clock, an internal 3. Superior Linearity. reference (and buffer), error correction circuits, and both serial No missing 16-bit code. ±1.5 LSB max INL. and parallel system interface ports. A falling edge on CNVST samples the analog input on IN+ with respect to a ground 4. Internal Reference. sense, IN−. The AD7612 features four different analog input 5 V internal reference with a typical drift of ±3 ppm/°C ranges and three different sampling modes: warp mode for the and an on-chip temperature sensor. fastest throughput, normal mode for the fastest asynchronous 5. Serial or Parallel Interface. throughput, and impulse mode where power consumption is Versatile parallel (16- or 8-bit bus) or 2-wire serial interface scaled linearly with throughput. Operation is specified from arrangement compatible with 3.3 V or 5 V logic. −40°C to +85°C.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V) (PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface MASTER SERIAL INTERFACE Internal Clock (SER/ = high, EXT/ = Low) Read During Convert (RDC = High) Read During Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) SLAVE SERIAL INTERFACE External Clock (SER/ = High, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE