Datasheet AD9230 (Analog Devices) - 8

AD9230 TIMING DIAGRAMS N – 1 t N + 4 A N + 5 N N + 3 VIN N + 1 N + 2 tCH tCL 1/fS CLK+ CLK– tCPD DCO+ DCO– tSKEW tPD DX+ N – 7 N – 6 N – 5 N – 4 N – 3
2 00
DX–
2- 00 06 Figure 2. Single Data Rate Mode
N – 1 t N + 4 A N + 5 N N + 3 VIN N + 1 N + 2 tCH tCL 1/fS CLK+ CLK– tCPD DCO+ DCO– tSKEW tPD D0/D6+ D6 D0 D6 D0 D6 D0 D6 D0 D6 D0 N – 8 N – 7 N – 7 N – 6 N – 6 N – 5 N – 5 N – 4 N – 4 N – 3 D0/D6– D5/D11+ D11 D5 D11 D5 D11 D5 D11 D5 D11 D5
3
N – 8 N – 7 N – 7 N – 6 N – 6 N – 5 N – 5 N – 4 N – 4 N – 3
-00 02
D5/D11–
060
6 MSBs 6 LSBs
Figure 3. Double Data Rate Mode Rev. 0 | Page 7 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS AD9230 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE