Datasheet AD9230 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter |
| Seiten / Seite | 33 / 9 — AD9230. ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating. THERMAL … |
| Dateiformat / Größe | PDF / 2.0 Mb |
| Dokumentensprache | Englisch |
AD9230. ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating. THERMAL RESISTANCE. Table 6. Package Type. θJA. θJC Unit. ESD CAUTION
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Textversion des Dokuments
AD9230 ABSOLUTE MAXIMUM RATINGS Table 5.
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress ELECTRICAL rating only; functional operation of the device at these or any AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational DRVDD to DRGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute AGND to DRGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect AVDD to DRVDD −2.0 V to +2.0 V device reliability. D0+/D0− through D13+/D13− −0.3 V to DRVDD + 0.3 V
THERMAL RESISTANCE
to DRGND The exposed paddle must be soldered to the ground plane for DCO to DRGND −0.3 V to DRVDD + 0.3 V the LFCSP package. Soldering the exposed paddle to the OR to DGND −0.3 V to DRVDD + 0.3 V customer board increases the reliability of the solder joints, CLK+ to AGND −0.3 V to +3.9 V maximizing the thermal capability of the package. CLK− to AGND −0.3 V to +3.9 V VIN+ to AGND −0.3 V to AVDD + 0.2 V
Table 6.
VIN− to AGND −0.3 V to AVDD + 0.2 V
Package Type θJA θJC Unit
SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V 56-Lead LFCSP (CP-48-3) 30.4 2.9 °C/W PDWN to AGND −0.3 V to +3.9 V CSB to AGND −0.3 V to +3.9 V Typical θJA and θJC are specified for a 4-layer board in still air. SCLK/DFS to AGND −0.3 V to +3.9 V Airflow increases heat dissipation, effectively reducing θJA. In ENVIRONMENTAL addition, metal in direct contact with the package leads from Storage Temperature Range −65°C to +125°C metal traces, and through holes, ground, and power planes Operating Temperature Range −40°C to +85°C reduces the θJA. Lead Temperature 300°C (Soldering 10 sec)
ESD CAUTION
Junction Temperature 150°C Rev. 0 | Page 8 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS AD9230 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress ELECTRICAL rating only; functional operation of the device at these or any AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational DRVDD to DRGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute AGND to DRGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect AVDD to DRVDD −2.0 V to +2.0 V device reliability. D0+/D0− through D13+/D13− −0.3 V to DRVDD + 0.3 V
THERMAL RESISTANCE
to DRGND The exposed paddle must be soldered to the ground plane for DCO to DRGND −0.3 V to DRVDD + 0.3 V the LFCSP package. Soldering the exposed paddle to the OR to DGND −0.3 V to DRVDD + 0.3 V customer board increases the reliability of the solder joints, CLK+ to AGND −0.3 V to +3.9 V maximizing the thermal capability of the package. CLK− to AGND −0.3 V to +3.9 V VIN+ to AGND −0.3 V to AVDD + 0.2 V
Table 6.
VIN− to AGND −0.3 V to AVDD + 0.2 V
Package Type θJA θJC Unit
SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V 56-Lead LFCSP (CP-48-3) 30.4 2.9 °C/W PDWN to AGND −0.3 V to +3.9 V CSB to AGND −0.3 V to +3.9 V Typical θJA and θJC are specified for a 4-layer board in still air. SCLK/DFS to AGND −0.3 V to +3.9 V Airflow increases heat dissipation, effectively reducing θJA. In ENVIRONMENTAL addition, metal in direct contact with the package leads from Storage Temperature Range −65°C to +125°C metal traces, and through holes, ground, and power planes Operating Temperature Range −40°C to +85°C reduces the θJA. Lead Temperature 300°C (Soldering 10 sec)
ESD CAUTION
Junction Temperature 150°C Rev. 0 | Page 8 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS AD9230 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE