Datasheet AD7767 (Analog Devices) - 7

AD7767 TIMING DIAGRAMS t2 1 8 × n 1 8 × n MCLK t3 t4 t1 t5 t5 DRDY tREAD
02 0 9-
tDRDY
85 06 Figure 2. DRDY vs. MCLK Timing Diagram, n = 1 for AD7767 (Decimate by 8), n = 2 for AD7767-1 (Decimate by 16), n = 4 for AD7767-2 (Decimate by 32)
tDRDY DRDY tREAD t t13 6 CS t10 1 23 SCLK t11 t8 t9 t7 t12
3 00
SDO MSB D22 D21 D20 D1 LSB
9- 85 06 Figure 3. Serial Timing Diagram, Reading Data Using CS
CS = 0 tDRDY DRDY tREAD t14 t10 SCLK 1 23 24 t11 t8 t9 t15 SDO DATA DATA MSB D22 D21 D20 D1 LSB INVALID INVALID
04 0 9- 85 06 Figure 4. Serial Timing Diagram, Reading Data Setting CS Logic Low Rev. C | Page 6 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION RELATED DEVICES TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION AD7767/AD7767-1/AD7767-2 TRANSFER FUNCTION CONVERTER OPERATION ANALOG INPUT STRUCTURE SUPPLY AND REFERENCE VOLTAGES AD7767 INTERFACE INITIAL POWER-UP READING DATA POWER-DOWN, RESET, AND SYNCHRONIZATION DAISY CHAINING READING DATA IN DAISY-CHAIN MODE CHOOSING THE SCLK FREQUENCY DAISY-CHAIN MODE CONFIGURATION AND TIMING DIAGRAMS DRIVING THE AD7767 DIFFERENTIAL SIGNAL SOURCE SINGLE-ENDED SIGNAL SOURCE ANTIALIASING POWER DISSIPATION VREF+ INPUT SIGNAL MULTIPLEXING ANALOG INPUT CHANNELS OUTLINE DIMENSIONS ORDERING GUIDE