Datasheet AD7767 (Analog Devices)

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24-Bit, 8.5 mW, 109 dB, 128 kSPS/64 kSPS/32 kSPS ADCs AD7767 FEATURES GENERAL DESCRIPTION Oversampled successive approximation (SAR) architecture
The AD7767/AD7767-1/AD7767-2 are high performance,
High performance ac and dc accuracy, low power
24-bit, oversampled SAR analog-to-digital converters (ADCs).
115.5 dB dynamic range, 32 kSPS (AD7767-2)
The AD7767/AD7767-1/AD7767-2 combine the benefits of a
112.5 dB dynamic range, 64 kSPS (AD7767-1)
large dynamic range and input bandwidth, consuming 15 mW,
109.5 dB dynamic range, 128 kSPS (AD7767)
10.5 mW, and 8.5 mW power, respectively, and are contained in
−118 dB THD
a 16-lead TSSOP package.
Exceptionally low power
Ideal for ultralow power data acquisition (such as PCI- and
8.5 mW, 32 kSPS (AD7767-2)
USB-based systems), the AD7767/AD7767-1/AD7767-2
10.5 mW, 64 kSPS (AD7767-1)
provide 24-bit resolution. The combination of exceptional SNR,
15 mW, 128 kSPS (AD7767)
wide dynamic range, and outstanding dc accuracy make the
High dc accuracy
AD7767/AD7767-1/AD7767-2 ideally suited for measuring
24 bits, no missing codes (NMC)
small signal changes over a wide dynamic range. This is
INL: ±3 ppm (typical), ±7.6 ppm (maximum)
particularly suitable for applications where small changes on the
Low temperature drift
input are measured on larger ac or dc signals. In such an
Zero error drift: 15 nV/°C
application, the AD7767/AD7767-1/AD7767-2 accurately
Gain error drift: 0.4 ppm/°C
gather both ac and dc information.
On-chip low-pass FIR filter Linear phase response
The AD7767/AD7767-1/AD7767-2 include an on-board digital
Pass-band ripple: ±0.005 dB
filter (complete with linear phase response) that acts to elimi-
Stop-band attenuation: 100 dB
nate out-of-band noise by filtering the oversampled input
2.5 V supply with 1.8 V/2.5 V/3 V/3.6 V logic interface options
voltage. The oversampled architecture also reduces front-end
Flexible interfacing options
antialias requirements. Other features of the AD7767 include a
Synchronization of multiple devices
SYNC/PD (synchronization/power-down) pin, allowing the
Daisy-chain capability
synchronization of multiple AD7767 devices. The addition of
Power-down function
an SDI pin provides the option of daisy chaining multiple
Temperature range: −40°C to +105°C
AD7767 devices.
APPLICATIONS
The AD7767/AD7767-1/AD7767-2 operate from a 2.5 V supply using a 5 V reference. The devices operate from −40°C to +105°C.
Low power PCI/USB data acquisition systems Low power wireless acquisition systems RELATED DEVICES Vibration analysis Table 1. 24-Bit ADCs Instrumentation High precision medical acquisition Part No. Description
AD7760 2.5 MSPS, 100 dB dynamic range,1 on-board differential
FUNCTIONAL BLOCK DIAGRAM
amp and reference buffer, parallel, variable decimation
AVDD AGND MCLK DVDD VDRIVE DGND
AD7762/ 625 kSPS, 109 dB dynamic range,1 on-board differential AD7763 amp and reference buffer, parallel/serial, variable
V
decimation
REF+ V
AD7764
IN+
312 kSPS, 109 dB dynamic range,1 on-board differential
SUCCESSIVE DIGITAL
amp and reference buffer, variable decimation (pin)
APPROXIMATION FIR FILTER ADC
AD7765 156 kSPS, 112 dB dynamic range,1 on-board differential
V SYNC/PD IN–
amp and reference buffer, variable decimation (pin)
SERIAL INTERFACE REFGND AND CS
AD7766 128 kSPS, 109.5 dB,1 15 mW, 16-bit INL, serial interface
CONTROL LOGIC AD7767/
AD7766-1 64 kSPS 112.5 dB,110.5 mW, 16-bit INL, serial interface
AD7767-1/ AD7767-2
AD7766-2 32 kSPS, 115.5 dB,1 8.5 mW, 16-bit INL, serial interface 1 00 9-
SCLK DRDY SDO SDI
85 1 06 Dynamic range at maximum output data rate. Figure 1.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION RELATED DEVICES TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION AD7767/AD7767-1/AD7767-2 TRANSFER FUNCTION CONVERTER OPERATION ANALOG INPUT STRUCTURE SUPPLY AND REFERENCE VOLTAGES AD7767 INTERFACE INITIAL POWER-UP READING DATA POWER-DOWN, RESET, AND SYNCHRONIZATION DAISY CHAINING READING DATA IN DAISY-CHAIN MODE CHOOSING THE SCLK FREQUENCY DAISY-CHAIN MODE CONFIGURATION AND TIMING DIAGRAMS DRIVING THE AD7767 DIFFERENTIAL SIGNAL SOURCE SINGLE-ENDED SIGNAL SOURCE ANTIALIASING POWER DISSIPATION VREF+ INPUT SIGNAL MULTIPLEXING ANALOG INPUT CHANNELS OUTLINE DIMENSIONS ORDERING GUIDE