Datasheet AD7264 (Analog Devices) - 9

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AD7264 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ND _G B A F + – + – _C ND ND CC A A B B A RE _G C C C C C V AG AV G0 G1 G2 G3 B A D 8 7 6 5 4 3 2 1 0 9 8 7 4 4 4 4 4 4 4 4 4 3 3 3 + – + – _C F N CC A A B B A RE C C C C C V AG AV G0 G1 G2 G3 C 1 36 CAL 48 47 46 45 44 43 42 41 40 39 38 37 A_CBVCC AV 2 35 CS CC V 3 34 SCLK C 1 36 CAL A– A_CBVCC PIN 1 V 4 33 AV A+ CC AV 2 INDICATOR 35 CS CC AGND 5 AD7264 32 DOUTA V 3 34 SCLK AGND 6 31 D A– OUTB TOP VIEW AV 7 30 C V 4 CC OUTA 33 AV (Not to Scale) A+ CC AGND 8 29 COUTB AGND 5 32 DOUTA V 9 28 DGND B+ AD7264 V 10 27 V AGND 6 31 D B– DRIVE TOP VIEW OUTB AV 11 26 C CC OUTC AVCC 7 (Not to Scale) 30 COUTA C 12 25 C C_CDVCC OUTD AGND 8 29 COUTB 3 4 5 6 7 8 9 0 1 2 3 4 V 9 28 DGND 1 1 1 1 1 1 1 2 2 2 2 2 B+ + – + – D B L 10 27 V V IN DRIVE C C D D CC B– F E C C C C N ND PD2 PD1 /D S AV RE 0 CC 11 26 C F OUTC _G AG AV D V C PD C_CDVCC 12 25 C RE OUTD _C C 13 14 15 16 17 18 19 20 21 22 23 24 C NOTES + – + – D B D 2 1
4
C C D D IN F CC 1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST C C C C N N PD PD /D SEL
-00
BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR
32
_G RE 0 AG AV F D V E NOISE AND MECHANICAL STRENGTH BENEFITS. PD
067
R
-003
_C
732
C
06
C
Figure 3. 48-Lead LQFP Pin Configuration Figure 4. 48-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
2, 7, 11, 20, 33, 41 AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the analog circuitry on the AD7264. All AVCC pins can be tied together. This supply should be decoupled to AGND with a 100 nF ceramic capacitor per supply and a 10 μF tantalum capacitor. 1 CA_CBVCC Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator A and Comparator B. This supply should be decoupled to CA_CB_GND. AVCC, CC_CDVCC, and CA_CBVCC can be tied together. 12 CC_CDVCC Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator C and Comparator D. This supply should be decoupled to CC_CD_GND. AVCC, CC_CDVCC, and CA_CBVCC can be tied together. 4, 3 VA+, VA− Analog Inputs of ADC A. True differential input pair. 9, 10 VB+, VB− Analog Inputs of ADC B. True differential input pair. 43, 18 VREFA, VREFB Reference Input/Output. Decoupling capacitors are connected to these pins to decouple the internal reference buffer for each respective ADC. Typically, 1 μF capacitors are required to decouple the reference. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. 34 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7264. This clock is also used as the clock source for the conversion process. A minimum of 33 clocks are required to perform the conversion and access the 14-bit result. 35 CS Chip Select. Active low logic input. This input initiates conversions on the AD7264. 36 CAL Logic Input. Initiates an internal offset calibration. 21 PD2 Logic Input. Places the AD7264 in the selected shutdown mode in conjunction with the PD1 and PD0 pins. See Table 7. 22 PD1 Logic Input. Places the AD7264 in the selected shutdown mode in conjunction with the PD2 and PD0 pins. See Table 7. 23 PD0/DIN Logic Input/Data Input. Places the AD7264 in the selected shutdown mode in conjunction with the PD2 and PD1 pins. See Table 7. If all gain selection pins, G0 to G3, are tied low, this pin acts as the data input pin and all programming is via the control register (see Table 8). Data to be written to the AD7264 control register is provided on this input and is clocked into the register on the falling edge of SCLK. Rev. D | Page 8 of 29 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTER SYSTEM GAIN CALIBRATION APPLICATIONS INFORMATION GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE