Datasheet AD9230-11 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 11-Bit, 200 MSPS, 1.8 V Analog-to-Digital Converter |
| Seiten / Seite | 29 / 7 — AD9230-11. SWITCHING SPECIFICATIONS. Table 4. Parameter. Temp. Min. Typ. … |
| Dateiformat / Größe | PDF / 665 Kb |
| Dokumentensprache | Englisch |
AD9230-11. SWITCHING SPECIFICATIONS. Table 4. Parameter. Temp. Min. Typ. Max. Unit
Modelllinie für dieses Datenblatt
Textversion des Dokuments
link to page 7 link to page 7
AD9230-11 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 4. Parameter Temp Min Typ Max Unit
CONVERSION RATE Maximum Conversion Rate Full 200 MSPS Minimum Conversion Rate Full 40 MSPS PULSE WIDTH CLK+ Pulse Width High (tCH) Full 2.25 2.5 ns CLK+ Pulse Width Low (tCL) Full 2.25 2.5 ns OUTPUT (LVDS, SDR MODE)1 Data Propagation Delay (tPD) Full 3.8 ns Rise Time (tR) (20% to 80%) 25°C 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 ns DCO Propagation Delay (tCPD) Full 3.9 ns Data to DCO Skew (tSKEW) Full −0.3 0.1 0.5 ns Latency Full 6 Cycles OUTPUT (LVDS, DDR MODE)2 Data Propagation Delay (tPD) Full 3.8 ns Rise Time (tR) (20% to 80%) 25°C 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 ns DCO Propagation Delay (tCPD) Full 3.9 ns Data to DCO Skew (tSKEW) Full −0.5 0.1 0.3 ns Latency Full 6 Cycles APERTURE UNCERTAINTY (JITTER, tJ) 25°C 0.2 ps rms 1 See Figur e 2. 2 See Figur e 3. Rev. 0 | Page 6 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS TRANSFER REGISTER MAP OUTLINE DIMENSIONS ORDERING GUIDE
AD9230-11 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 4. Parameter Temp Min Typ Max Unit
CONVERSION RATE Maximum Conversion Rate Full 200 MSPS Minimum Conversion Rate Full 40 MSPS PULSE WIDTH CLK+ Pulse Width High (tCH) Full 2.25 2.5 ns CLK+ Pulse Width Low (tCL) Full 2.25 2.5 ns OUTPUT (LVDS, SDR MODE)1 Data Propagation Delay (tPD) Full 3.8 ns Rise Time (tR) (20% to 80%) 25°C 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 ns DCO Propagation Delay (tCPD) Full 3.9 ns Data to DCO Skew (tSKEW) Full −0.3 0.1 0.5 ns Latency Full 6 Cycles OUTPUT (LVDS, DDR MODE)2 Data Propagation Delay (tPD) Full 3.8 ns Rise Time (tR) (20% to 80%) 25°C 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 ns DCO Propagation Delay (tCPD) Full 3.9 ns Data to DCO Skew (tSKEW) Full −0.5 0.1 0.3 ns Latency Full 6 Cycles APERTURE UNCERTAINTY (JITTER, tJ) 25°C 0.2 ps rms 1 See Figur e 2. 2 See Figur e 3. Rev. 0 | Page 6 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS TRANSFER REGISTER MAP OUTLINE DIMENSIONS ORDERING GUIDE