Datasheet AD7190 (Analog Devices) - 6

HerstellerAnalog Devices
Beschreibung4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA
Seiten / Seite41 / 6 — Data Sheet. AD7190. Parameter. AD7190B. Unit. Test Conditions/Comments1
RevisionC
Dateiformat / GrößePDF / 689 Kb
DokumentenspracheEnglisch

Data Sheet. AD7190. Parameter. AD7190B. Unit. Test Conditions/Comments1

Data Sheet AD7190 Parameter AD7190B Unit Test Conditions/Comments1

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Data Sheet AD7190 Parameter AD7190B Unit Test Conditions/Comments1
Normal Mode Rejection2 Same as for analog inputs Common-Mode Rejection 95 dB typ Reference Detect Levels 0.3 V min 0.6 V max TEMPERATURE SENSOR Accuracy ±2 °C typ Applies after user calibration at 25°C. Sensitivity 2815 Codes/°C typ Bipolar mode. BRIDGE POWER-DOWN SWITCH RON 10 Ω max Allowable Current2 30 mA max Continuous current. BURNOUT CURRENTS AIN Current 500 nA nom Analog inputs must be buffered and chop disabled. DIGITAL OUTPUTS (P0 to P3) Output High Voltage, V 2 OH 4 V min AVDD = 5V, ISOURCE = 200 μA. Output Low Voltage, V 2 OL 0.4 V max AVDD = 5V, ISINK = 800 μA. Floating-State Leakage Current ±100 nA max Floating-State Output 10 pF typ Capacitance INTERNAL/EXTERNAL CLOCK Internal Clock Frequency 4.92 ± 4% MHz min/max Duty Cycle 50:50 % typ External Clock/Crystal2 Frequency 4.9152 MHz nom 2.4576/5.12 MHz min/max Input Low Voltage, VINL 0.8 V max DVDD = 5 V. 0.4 V max DVDD = 3 V. Input High Voltage, VINH 2.5 V min DVDD = 3 V. 3.5 V min DVDD = 5 V. Input Current ±10 μA max LOGIC INPUTS Input High Voltage, V 2 INH 2 V min Input Low Voltage, V 2 INL 0.8 V max Hysteresis2 0.1/0.25 V min/V max Input Currents ±10 μA max LOGIC OUTPUT (DOUT/RDY) Output High Voltage, V 2 OH DVDD − 0.6 V min DVDD = 3 V, ISOURCE = 100 μA. Output Low Voltage, V 2 OL 0.4 V max DVDD = 3 V, ISINK = 100 μA. Output High Voltage, V 2 OH 4 V min DVDD = 5 V, ISOURCE = 200 μA. Output Low Voltage, V 2 OL 0.4 V max DVDD = 5 V, ISINK = 1.6 mA. Floating-State Leakage Current ±10 μA max Floating-State Output 10 pF typ Capacitance Data Output Coding Offset binary SYSTEM CALIBRATION2 Full-Scale Calibration Limit 1.05 × FS V max Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max Rev. C | Page 5 of 40 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Characteristics Circuit and Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics RMS Noise and Resolution Sinc4 Chop Disabled Sinc3 Chop Disabled Sinc4 Chop Enabled Sinc3 Chop Enabled On-Chip Registers Communications Register Status Register Mode Register Configuration Register Data Register ID Register GPOCON Register Offset Register Full-Scale Register ADC Circuit Information Overview Filter, Output Data Rate, Settling Time Chop Disabled Chop Enabled 50 Hz/60 Hz Rejection Zero Latency Channel Sequencer Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Circuit Description Analog Input Channel PGA Bipolar/Unipolar Configuration Data Output Coding Clock Burnout Currents Reference Reference Detect Reset System Synchronization Temperature Sensor Bridge Power-Down Switch Logic Outputs Enable Parity Calibration Grounding and Layout Applications Information Weigh Scales Outline Dimensions Ordering Guide Automotive Products