Datasheet AD7192 (Analog Devices) - 7

link to page 7 link to page 7
AD7192 Parameter AD7192B Unit Test Conditions/Comments1
SYSTEM CALIBRATION2 Full-Scale Calibration Limit 1.05 × FS V max Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max POWER REQUIREMENTS7 Power Supply Voltage AVDD − AGND 3/5.25 V min/max DVDD − DGND 2.7/5.25 V min/max Power Supply Currents AIDD Current 0.6 mA max 0.53 mA typical, gain = 1, buffer off. 0.85 mA max 0.75 mA typical, gain = 1, buffer on. 3.2 mA max 2.5 mA typical, gain = 8, buffer off. 3.6 mA max 3 mA typical, gain = 8, buffer on. 4.5 mA max 3.5 mA typical, gain = 16 to 128, buffer off. 5 mA max 4 mA typical, gain = 16 to 128, buffer on. DIDD Current 0.4 mA max 0.35 mA typical, DVDD = 3 V. 0.6 mA max 0.5 mA typical, DVDD = 5 V. 1.5 mA typ External crystal used. IDD (Power-Down Mode) 3 μA max 1 Temperature range: −40°C to +105°C. 2 Specification is not production tested but is supported by characterization data at initial product release. 3 FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full- scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 5 The analog inputs are configured for differential mode. 6 REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection. 7 Digital inputs equal to DVDD or DGND. Rev. A | Page 6 of 40 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS CIRCUIT AND TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW FILTER, OUTPUT DATA RATE, AND SETTLING TIME Chop Disabled Chop Enabled 50 Hz/60Hz Rejection Zero Latency Channel Sequencer Single Conversion Mode Continuous Conversion Mode Continuous Read CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL PROGRAMMABLE GAIN ARRAY (PGA) BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING CLOCK BURNOUT CURRENTS REFERENCE REFERENCE DETECT RESET SYSTEM SYNCHRONIZATION TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS ENABLE PARITY CALIBRATION GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE