Datasheet AD7192 (Analog Devices)

4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA AD7192 FEATURES Temperature measurement RMS noise: 11 nV @ 4.7 Hz (gain = 128) Chromatography 15.5 noise-free bits @ 2.4 kHz (gain = 128) PLC/DCS analog input modules Up to 22 noise-free bits (gain = 1) Data acquisition Offset drift: 5 nV/°C Medical and scientific instrumentation Gain drift: 1 ppm/°C GENERAL DESCRIPTION Specified drift over time
The AD7192 is a low noise, complete analog front end for high
2 differential/4 pseudo differential input channels
precision measurement applications. It contains a low noise,
Automatic channel sequencer
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
Programmable gain (1 to 128)
The on-chip low noise gain stage means that signals of small
Output data rate: 4.7 Hz to 4.8 kHz
amplitude can be interfaced directly to the ADC.
Internal or external clock Simultaneous 50 Hz/60 Hz rejection
The device can be configured to have two differential inputs or
4 general-purpose digital outputs
four pseudo differential inputs. The on-chip channel sequencer
Power supply
allows several channels to be enabled, and the AD7192 sequentially
AVDD: 3 V to 5.25 V
converts on each enabled channel. This simplifies communication
DVDD: 2.7 V to 5.25 V
with the part. The on-chip 4.92 MHz clock can be used as the
Current: 4.35 mA
clock source to the ADC or, alternatively, an external clock or
Temperature range: –40°C to +105°C
crystal can be used. The output data rate from the part can be
Package: 24-lead TSSOP
varied from 4.7 Hz to 4.8 kHz.
INTERFACE
The device has two digital filter options. The choice of filter affects the rms noise/noise-free resolution at the programmed
3-wire serial
output data rate, the settling time, and the 50 Hz/60 Hz
SPI, QSPI™, MICROWIRE™, and DSP compatible
rejection. For applications that require all conversions to be
Schmitt trigger on SCLK
settled, the AD7192 includes a zero latency feature.
APPLICATIONS
The part operates with a power supply from 3 V to 5.25 V. It
Weigh scales
consumes a current of 4.35 mA. It is housed in a 24-lead TSSOP
Strain gage transducers
package.
Pressure measurement FUNCTIONAL BLOCK DIAGRAM AGND AV DV DD DD DGND REFIN1(+) REFIN1(–) REFERENCE AD7192 DETECT AV AIN1 DD AIN2 AIN3 SERIAL DOUT/RDY AIN4 INTERFACE AINCOM MUX Σ-Δ DIN PGA AND ADC CONTROL SCLK LOGIC CS SYNC AGND TEMP P3 SENSOR BPDSW P2 CLOCK CIRCUITRY AGND
01 0 2-
MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)
82 07 Figure 1.
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Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS CIRCUIT AND TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW FILTER, OUTPUT DATA RATE, AND SETTLING TIME Chop Disabled Chop Enabled 50 Hz/60Hz Rejection Zero Latency Channel Sequencer Single Conversion Mode Continuous Conversion Mode Continuous Read CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL PROGRAMMABLE GAIN ARRAY (PGA) BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING CLOCK BURNOUT CURRENTS REFERENCE REFERENCE DETECT RESET SYSTEM SYNCHRONIZATION TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS ENABLE PARITY CALIBRATION GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE