Datasheet AD7192 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | 4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA |
| Seiten / Seite | 41 / 3 — AD7192. TABLE OF CONTENTS. REVISION HISTORY. 5/09—Rev. 0 to Rev. A. … |
| Revision | A |
| Dateiformat / Größe | PDF / 566 Kb |
| Dokumentensprache | Englisch |
AD7192. TABLE OF CONTENTS. REVISION HISTORY. 5/09—Rev. 0 to Rev. A. 5/09—Revision 0: Initial Version
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AD7192 TABLE OF CONTENTS
Features .. 1 Offset Register .. 24 Interface ... 1 Full-Scale Register .. 24 Applications ... 1 ADC Circuit Information .. 25 General Description ... 1 Overview ... 25 Functional Block Diagram .. 1 Filter, Output Data Rate, and Settling Time ... 25 Revision History ... 2 Digital Interface .. 28 Specifications ... 3 Circuit Description... 32 Timing Characteristics ... 7 Analog Input Channel ... 32 Circuit and Timing Diagrams ... 7 Programmable Gain Array (PGA) ... 32 Absolute Maximum Ratings .. 9 Bipolar/Unipolar Configuration .. 32 Thermal Resistance .. 9 Data Output Coding .. 32 ESD Caution .. 9 Clock .. 32 Pin Configuration and Function Descriptions ... 10 Burnout Currents ... 33 Typical Performance Characteristics ... 12 Reference ... 33 RMS Noise and Resolution .. 14 Reference Detect ... 33 Sinc4 Chop Disabled ... 14 Reset ... 34 Sinc3 Chop Disabled ... 15 System Synchronization .. 34 Sinc4 Chop Enabled .. 16 Temperature Sensor ... 34 Sinc3 Chop Enabled .. 17 Bridge Power-Down Switch .. 34 On-Chip Registers .. 18 Logic Outputs ... 34 Communications Register ... 18 Enable Parity ... 35 Status Register ... 19 Calibration ... 35 Mode Register ... 19 Grounding and Layout .. 36 Configuration Register .. 21 Applications Information .. 37 Data Register ... 23 Weigh Scales .. 37 ID Register ... 23 Outline Dimensions ... 38 GPOCON Register ... 24 Ordering Guide .. 38
REVISION HISTORY 5/09—Rev. 0 to Rev. A
Change to Gain Error Specification ... 3 Changes to Table 3 .. 9
5/09—Revision 0: Initial Version
Rev. A | Page 2 of 40 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS CIRCUIT AND TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW FILTER, OUTPUT DATA RATE, AND SETTLING TIME Chop Disabled Chop Enabled 50 Hz/60Hz Rejection Zero Latency Channel Sequencer Single Conversion Mode Continuous Conversion Mode Continuous Read CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL PROGRAMMABLE GAIN ARRAY (PGA) BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING CLOCK BURNOUT CURRENTS REFERENCE REFERENCE DETECT RESET SYSTEM SYNCHRONIZATION TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS ENABLE PARITY CALIBRATION GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE
AD7192 TABLE OF CONTENTS
Features .. 1 Offset Register .. 24 Interface ... 1 Full-Scale Register .. 24 Applications ... 1 ADC Circuit Information .. 25 General Description ... 1 Overview ... 25 Functional Block Diagram .. 1 Filter, Output Data Rate, and Settling Time ... 25 Revision History ... 2 Digital Interface .. 28 Specifications ... 3 Circuit Description... 32 Timing Characteristics ... 7 Analog Input Channel ... 32 Circuit and Timing Diagrams ... 7 Programmable Gain Array (PGA) ... 32 Absolute Maximum Ratings .. 9 Bipolar/Unipolar Configuration .. 32 Thermal Resistance .. 9 Data Output Coding .. 32 ESD Caution .. 9 Clock .. 32 Pin Configuration and Function Descriptions ... 10 Burnout Currents ... 33 Typical Performance Characteristics ... 12 Reference ... 33 RMS Noise and Resolution .. 14 Reference Detect ... 33 Sinc4 Chop Disabled ... 14 Reset ... 34 Sinc3 Chop Disabled ... 15 System Synchronization .. 34 Sinc4 Chop Enabled .. 16 Temperature Sensor ... 34 Sinc3 Chop Enabled .. 17 Bridge Power-Down Switch .. 34 On-Chip Registers .. 18 Logic Outputs ... 34 Communications Register ... 18 Enable Parity ... 35 Status Register ... 19 Calibration ... 35 Mode Register ... 19 Grounding and Layout .. 36 Configuration Register .. 21 Applications Information .. 37 Data Register ... 23 Weigh Scales .. 37 ID Register ... 23 Outline Dimensions ... 38 GPOCON Register ... 24 Ordering Guide .. 38
REVISION HISTORY 5/09—Rev. 0 to Rev. A
Change to Gain Error Specification ... 3 Changes to Table 3 .. 9
5/09—Revision 0: Initial Version
Rev. A | Page 2 of 40 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS CIRCUIT AND TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW FILTER, OUTPUT DATA RATE, AND SETTLING TIME Chop Disabled Chop Enabled 50 Hz/60Hz Rejection Zero Latency Channel Sequencer Single Conversion Mode Continuous Conversion Mode Continuous Read CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL PROGRAMMABLE GAIN ARRAY (PGA) BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING CLOCK BURNOUT CURRENTS REFERENCE REFERENCE DETECT RESET SYSTEM SYNCHRONIZATION TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS ENABLE PARITY CALIBRATION GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE