Datasheet AD9251 (Analog Devices) - 5

AD9251 Data Sheet SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
Table 1. AD9251-20/AD9251-40 AD9251-65 AD9251-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.1 ±0.70 ±0.1 ±0.50 ±0.1 ±0.70 % FSR Gain Error1 Full −1.5 −1.5 −1.5 % FSR Differential Nonlinearity (DNL)2 Full ±0.60 ±0.75 ±0.70 LSB 25°C ±0.3 ±0.45 ±0.45 LSB Integral Nonlinearity (INL)2 Full ±1.75 ±1.75 ±2.50 LSB 25°C ±0.6 ±0.6 ±1.0 LSB MATCHING CHARACTERISTICS Offset Error 25°C ±0.0 ±0.65 ±0.0 ±0.65 ±0.0 ±0.65 % FSR Gain Error1 25°C ±0.2 ±0.2 ±0.2 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.981 0.993 1.005 0.981 0.993 1.005 0.981 0.993 1.005 V Load Regulation Error at 1.0 mA Full 2 2 2 mV INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0.98 0.98 0.98 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance3 Full 6 6 6 pF Input Common-Mode Voltage Full 0.9 0.9 0.9 V Input Common-Mode Range Full 0.5 1.3 0.5 1.3 0.5 1.3 V REFERENCE INPUT RESISTANCE Full 7.5 7.5 7.5 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current IAVDD2 Full 36.5/49.5 39.4/52.8 69.0 72.9 80.5 85.5 mA IDRVDD2 (1.8 V) Full 3.4/5.6 8.4 10.3 mA IDRVDD2 (3.3 V) Full 6.3/10.6 16.0 19.5 mA POWER CONSUMPTION DC Input Full 66/89 125 145 mW Sine Wave Input2 (DRVDD = 1.8 V) Full 71.8/99 77.0/105.5 139.0 146.5 163.4 173 mW Sine Wave Input2 (DRVDD = 3.3 V) Full 86.5/124 176.7 209 mW Standby Power4 Full 37 37 37 mW Power-Down Power Full 2.2 2.2 2.2 mW 1 Measured with 1.0 V external reference. 2 Measured with a 10 MHz input frequency at rated sample rate, ful -scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input and the CLK active. Rev. B | Page 4 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9251-80 AD9251-65 AD9251-40 AD9251-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE