Datasheet AD9251 (Analog Devices) - 4

Data Sheet AD9251 GENERAL DESCRIPTION
The AD9251 is a monolithic, dual-channel, 1.8 V supply, A differential clock input controls al internal conversion cycles. 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital An optional duty cycle stabilizer (DCS) compensates for wide converter (ADC). It features a high performance sample-and- variations in the clock duty cycle while maintaining excel ent hold circuit and on-chip voltage reference. overal ADC performance. The product uses multistage differential pipeline architecture The digital output data is presented in offset binary, gray code, with output error correction logic to provide 14-bit accuracy at or twos complement format. A data output clock (DCO) is 80 MSPS data rates and to guarantee no missing codes over the provided for each ADC channel to ensure proper latch timing full operating temperature range. with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single The ADC contains several features designed to maximize output bus. flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern The AD9251 is available in a 64-lead RoHS Compliant LFCSP generation. The available digital test patterns include built-in and is specified over the industrial temperature range (−40°C deterministic and pseudorandom patterns, along with custom to +85°C). user-defined test patterns entered via the serial port interface (SPI). Rev. B | Page 3 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9251-80 AD9251-65 AD9251-40 AD9251-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE