Datasheet AD9265 (Analog Devices) - 2

AD9265* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS
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Solutions Bulletins & Brochures
• Analog-to-Digital Converter and Drivers ICs Solutions
EVALUATION KITS
Bulletin, Volume 10, Issue 2 • AD9265 Evaluation Board
Technical Articles
• Improve The Design Of Your Passive Wideband ADC
DOCUMENTATION
Front-End Network
Data Sheet
• MS-2210: Designing Power Supplies for High Speed ADC • AD9265: 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V • The Differential-signal Advantage for Communications Analog-to-Digital Converter Data Sheet System Design
User Guides DESIGN RESOURCES
• UG-074: Evaluating the AD9265/AD9255 Analog-to- Digital Converters • AD9265 Material Declaration • PCN-PDN Information
SOFTWARE AND SYSTEMS REQUIREMENTS
• Quality And Reliability • AD9265 Native FMC Card / ML605 Xilinx Reference Design • Symbols and Footprints
TOOLS AND SIMULATIONS DISCUSSIONS
• Visual Analog View all AD9265 EngineerZone Discussions. • AD9265 IBIS Models • AD9255/AD9265 S-Parameters
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REFERENCE DESIGNS
• CN0252
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Document Outline Features Applications Product Highlights Functional Block Diagram Table of Contents Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Dither Large Signal FFT Small Signal FFT Static Linearity Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Clock Duty Cycle Input Clock Divider Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Applications Information Design Guidelines Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide