Datasheet AD9265 (Analog Devices)

16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9265 FEATURES PRODUCT HIGHLIGHTS SNR = 79.0 dBFS at 70 MHz and 125 MSPS
1. On-chip dither option for improved SFDR performance
SFDR = 93 dBc at 70 MHz and 125 MSPS
with low power analog input.
Low power: 373 mW at 125 MSPS
2. Proprietary differential input that maintains excel ent SNR
1.8 V analog supply operation
performance for input frequencies up to 300 MHz.
1.8 V CMOS or LVDS output supply
3. Operation from a single 1.8 V supply and a separate digital
Integer 1-to-8 input clock divider
output driver supply accommodating 1.8 V CMOS or
IF sampling frequencies to 300 MHz
LVDS outputs.
−154.3 dBm/Hz small signal input noise with 200 Ω input
4. Standard serial port interface (SPI) that supports various
impedance at 70 MHz and 125 MSPS
product features and functions, such as data formatting
Optional on-chip dither
(offset binary, twos complement, or gray coding), enabling
Programmable internal ADC voltage reference
the clock duty cycle stabilizer, DCS, power-down, test
Integrated ADC sample-and-hold inputs
modes, and voltage reference mode.
Flexible analog input range: 1 V p-p to 2 V p-p
5. Pin compatibility with the AD9255, al owing a simple
Differential analog inputs with 650 MHz bandwidth
migration from 16 bits down to 14 bits.
ADC clock duty cycle stabilizer Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes APPLICATIONS Communications Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment FUNCTIONAL BLOCK DIAGRAM SENSE RBIAS PDWN AGND AVDD (1.8V) LVDS LVDS_RS REFERENCE VREF AD9265 VCM DRVDD (1.8V) VIN+ TRACK-AND-HOLD VIN– OUTPUT ADC 16 STAGING 16 DITHER 16-BIT CMOS OR D15 TO D0 CORE LVDS (DDR) CLK+ CLOCK OR CLK– MANAGEMENT SYNC SERIAL PORT DCO
001
SVDD SCLK/ SDIO/ CSB DFS DCS
08502- Figure 1.
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Document Outline Features Applications Product Highlights Functional Block Diagram Table of Contents Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Dither Large Signal FFT Small Signal FFT Static Linearity Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Clock Duty Cycle Input Clock Divider Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Memory Map Register Table Memory Map Register Descriptions Sync Control (Register 0x100) Applications Information Design Guidelines Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide