Datasheet AD9261 (Analog Devices) - 10

AD9261 TYPICAL PERFORMANCE CHARACTERISTICS
All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, TA = 25°C, unless otherwise noted.
0 0 BANDWIDTH: 2.5MHz BANDWIDTH: 2.5MHz –20 DATA RATE: 40MSPS –20 DATA RATE: 40MSPS fIN: 600kHz AT –2dBFS fIN1: 2.1MHz AT –8dBFS SNR: 88.8dB fIN2: 2.5MHz AT –8dBFS –40 SFDR: 90dBc –40 SFDR: 90.6dBc ) ) S S –60 BF –60 BF d d ( ( E –80 –80 UDE UD IT IT L L P –100 P –100 M A AM –120 –120 –140 –140 –160
1
–160
52
0 2 4 6 8 10 12 14 16 18 20
01
0 2 4 6 8 10 12 14 16 18 20
0 3- 3-
FREQUENCY (MHz)
80
FREQUENCY (MHz)
780 07 0 Figure 4. Single-Tone FFT with fIN = 600 kHz and BW = 2.5 MHz Figure 6. Two-Tone FFT with fIN1 = 2.1 MHz, fIN2 = 2.5 MHz, and BW = 2.5 MHz
0 0 BANDWIDTH: 5MHz BANDWIDTH: 5MHz DATA RATE: 40MSPS –20 DATA RATE: 40MSPS –20 f f IN: 1.2MHz AT –2dBFS IN1: 2.1MHz AT –8dBFS SNR: 86dB fIN2: 2.4MHz AT –8dBFS –40 –40 SFDR: 90.3dBc SFDR: 91.9dBc ) ) S S –60 BF –60 BF d d ( ( –80 –80 UDE UDE IT IT L L P –100 P –100 M M A A –120 –120 –140 –140 –160
5
–160
3
0 2 4 6 8 10 12 14 16 18 20
01
0 2 4 6 8 10 12 14 16 18 20
05 3- 3- 80
FREQUENCY (MHz)
80
FREQUENCY (MHz)
07 07 Figure 5. Single-Tone FFT with fIN = 1.2 MHz and BW = 5 MHz Figure 7. Two-Tone FFT with fIN1 = 2.1 MHz, fIN2 = 2.4 MHz and BW = 5 MHz Rev. 0 | Page 9 of 28 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Memory Map Memory Map Definitions Outline Dimensions Ordering Guide