Datasheet AD9628 (Analog Devices) - 6

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Data Sheet AD9628 AD9628-105 AD9628-125 Parameter Temp Min Typ Max Min Typ Max Unit
POWER CONSUMPTION DC Input Full 129 148 mW Sine Wave Input (DRVDD = 1.8 V CMOS Full 173 182 201 212 mW Output Mode)1 Sine Wave Input (DRVDD = 1.8 V LVDS Full 243 269 mW Output Mode)1 Standby Power3 Full 108 120 mW Power-Down Power Full 2.0 2.0 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode).
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.
Table 2. AD9628-105 AD9628-125 Parameter1 Temp Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR) fIN = 9.7 MHz 25°C 71.6 71.5 dBFS fIN = 30.5 MHz 25°C 71.6 71.4 dBFS fIN = 70 MHz 25°C 71.3 71.2 dBFS Full 70.6 70.2 dBFS fIN = 100 MHz 25°C 71.0 70.9 dBFS fIN = 200 MHz 25°C 69.4 69.6 dBFS SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 9.7 MHz 25°C 71.5 71.4 dBFS fIN = 30.5 MHz 25°C 71.5 71.3 dBFS fIN = 70 MHz 25°C 71.2 71.1 dBFS Full 70.5 70 dBFS fIN = 100 MHz 25°C 69.9 69.8 dBFS fIN = 200 MHz 25°C 68.1 68.3 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 11.6 11.6 Bits fIN = 30.5 MHz 25°C 11.6 11.6 Bits fIN = 70 MHz 25°C 11.6 11.5 Bits fIN = 100 MHz 25°C 11.5 11.3 Bits fIN = 200 MHz 25°C 11.0 11.1 Bits WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −92 −92 dBc fIN = 30.5 MHz 25°C −90 −90 dBc fIN = 70 MHz 25°C −90 −93 dBc Full −82 −85 dBc fIN = 100 MHz 25°C −89 −90 dBc fIN = 200 MHz 25°C −83 −84 dBc Rev. C | Page 5 of 42 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9628-125 AD9628-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bits[7:6]—Output Port Logic Type Bit 5—Output Interleave Enable Bit 4—Output Port Disable Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Open Transfer (Register 0xFF) Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable Bits[6:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Clock Stability Considerations Exposed Paddle Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE