Datasheet AD9253 (Analog Devices) - 2

AD9253* PRODUCT PAGE QUICK LINKS Last Content Update: 09/27/2017 COMPARABLE PARTS TOOLS AND SIMULATIONS
View a parametric search of comparable parts. • Visual Analog • AD9253 IBIS Model
EVALUATION KITS
• AD9253 Evaluation Board
REFERENCE DESIGNS
• CN0249
DOCUMENTATION Application Notes REFERENCE MATERIALS
• AN-1142: Techniques for High Speed ADC PCB Layout
Technical Articles
• AN-501: Aperture Uncertainty and ADC System • MS-2210: Designing Power Supplies for High Speed ADC Performance
Tutorials
• AN-737: How ADIsimADC Models an ADC • MT-230: Noise Considerations in High Speed Converter • AN-742: Frequency Domain Response of Switched- Signal Chains Capacitor ADCs • AN-756: Sampled Systems and the Effects of Clock Phase
DESIGN RESOURCES
Noise and Jitter • AD9253 Material Declaration • AN-807: Multicarrier WCDMA Feasibility • PCN-PDN Information • AN-808: Multicarrier CDMA2000 Feasibility • Quality And Reliability • AN-827: A Resonant Approach to Interfacing Amplifiers to • Symbols and Footprints Switched-Capacitor ADCs • AN-835: Understanding High Speed ADC Testing and
DISCUSSIONS
Evaluation • AN-878: High Speed ADC SPI Control Software View all AD9253 EngineerZone Discussions. • AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual
SAMPLE AND BUY
• AN-935: Designing an ADC Transformer-Coupled Front Visit the product page to see pricing options. End
Data Sheet TECHNICAL SUPPORT
• AD9253-DSCC: Military Data Sheet Submit a technical question or find your regional support • AD9253-EP: Enhanced Product Data Sheet number. • AD9253: Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter
DOCUMENT FEEDBACK User Guides
Submit feedback for this data sheet. • Evaluating the AD9253/AD9633/AD9653 Analog-to- Digital Converters
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9253-80 AD9253-105 AD9253-125 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Crosstalk Performance Outline Dimensions Ordering Guide