Datasheet AD9253 (Analog Devices) - 4

Data Sheet AD9253 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 1. AD9253-80 AD9253-105 AD9253-125 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 14 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full −0.7 −0.3 +0.1 −0.7 −0.3 +0.1 −0.7 −0.3 +0.1 % FSR Offset Matching Full −0.6 +0.2 +0.6 −0.6 +0.2 +0.6 −0.6 +0.2 +0.6 % FSR Gain Error Full −10 −5 0 −10 −5 0 −10 −5 0 % FSR Gain Matching Full 1 1.6 1 1.6 1.1 1.6 % FSR Differential Nonlinearity (DNL) Full −1 +1.6 −0.8 +1.5 −0.8 +1.5 LSB 25°C ±0.8 ±0.75 ±0.75 LSB Integral Nonlinearity (INL) Full −4.0 +4.0 −4.0 4.0 −4.0 +4.0 LSB 25°C ±1.5 ±2.0 ±2.0 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.98 1.0 1.02 0.98 1.0 1.02 0.98 1.0 1.02 V Load Regulation at 1.0 mA (VREF = 1 V) Full 2 2 2 mV Input Resistance Full 7.5 7.5 7.5 kΩ INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0. 94 0. 94 0. 94 LSB rms ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Full 2 2 2 V p-p Common-Mode Voltage Full 0.9 0.9 0.9 V Differential Input Resistance 5.2 5.2 5.2 kΩ Differential Input Capacitance Full 3.5 3.5 3.5 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V I 2 AVDD Full 131 144 158 172 183 200 mA IDRVDD (ANSI-644 Mode)2 Full 63 81 67 95 71 100 mA IDRVDD (Reduced Range Mode)2 25°C 42 48 53 mA TOTAL POWER CONSUMPTION DC Input Full 326 375 423 mW Sine Wave Input (Four Channels Including Full 349 405 405 481 457 540 mW Output Drivers ANSI-644 Mode) Sine Wave Input (Four Channels Including 25°C 311 371 425 mW Output Drivers Reduced Range Mode) Power-Down Full 2 2 2 mW Standby3 Full 178 209 236 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured with a low input frequency, full-scale sine wave on all four channels. 3 Can be controlled via the SPI. Rev. B | Page 3 of 40 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9253-80 AD9253-105 AD9253-125 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Crosstalk Performance Outline Dimensions Ordering Guide