Datasheet AD9653 (Analog Devices) - 4

HerstellerAnalog Devices
BeschreibungQuad, 16-Bit, 125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter
Seiten / Seite42 / 4 — Data Sheet. AD9653. REVISION HISTORY 3/16—Rev. D to Rev. E. 11/14—Rev. 0 …
RevisionF
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DokumentenspracheEnglisch

Data Sheet. AD9653. REVISION HISTORY 3/16—Rev. D to Rev. E. 11/14—Rev. 0 to Rev. A. 11/15—Rev. C to Rev. D. 8/15—Rev. B to Rev. C

Data Sheet AD9653 REVISION HISTORY 3/16—Rev D to Rev E 11/14—Rev 0 to Rev A 11/15—Rev C to Rev D 8/15—Rev B to Rev C

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Data Sheet AD9653 REVISION HISTORY 3/16—Rev. D to Rev. E 11/14—Rev. 0 to Rev. A
Changes to General Description Section ... 1 Changed Output Voltage (1.0 V Mode) from 1.01 V to Changes to Figure 15 .. 15 1.02 V (max); Table 1 .. 3 Changes to Table 13 .. 29 Changes to Table 3 .. 5 Added tPD of 1.5 ns (min) and 3.1 ns (max); Table 6 .. 8
11/15—Rev. C to Rev. D
Changed tSSYNC from 0.24 ns (typ) to 1.2 ns (min) and Changed Changes to General Description Section ... 1 tHSYNC from 0.40 ns (typ) to −0.2 ns (min); Table 7 ... 9 Added Note 4, Table 6 ... 8 Changes to Table 10 .. 12 Changes to Digital Outputs and Timing Section .. 28 Changes to Clock Input Options Section .. 24 Changes to Digital Outputs and Timing Section .. 27
8/15—Rev. B to Rev. C
Changes to Table 13 .. 28 Change to Applications Section .. 1 Changes to Table 14 .. 29 Change to Jitter Considerations Section .. 25 Changes to Channel-Specific Registers Section ... 32 Changes to Register 0x14 Bit 1 and Default Value ... 34
7/15—Rev. A to Rev. B
Changes to Register 0x16; Bits[6:4]—Input Clock Phase Adjust Added Patent Note, Note 1... 1 Section and Sample Rate Override (Register 0x100) Section ... 37 Change to Applications Section and General Description Added Clock Stability Considerations Section ... 38 Section .. 1 Change to Effective Number of Bits (ENOB) Parameter,
5/12—Revision 0: Initial Version
Table 3 ... 5 Changes to Table 5 .. 7 Change to Table 8 .. 11 Changes to Reading the Memory Map Register Table Section and Channel-Specific Registers Section ... 32 Changes to Table 19 .. 33 Changes to Device Index (Register 0x04, Register 0x05) Section .. 36 Changes to Clock Stability Considerations Section.. 38 Rev. E | Page 3 of 41 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.3 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x04, Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Clock (Register 0x09) Bits[7:1]—Open Bit 0—Duty Cycle Stabilize Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—1 Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Sample Rate Override (Register 0x100) User Input/Output Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User Input/Output Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT CROSSTALK PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE