Datasheet AD9653 (Analog Devices)

Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter Data Sheet AD9653 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V supply operation AVDD PDWN DRVDD Low power: 164 mW per channel at 125 MSPS SERIAL D0+A SNR = 76.5 dBFS at 70 MHz (2.0 V p-p input span) VIN+A 16 PIPELINE DIGITAL LVDS D0–A VIN–A ADC SERIALIZER SNR = 77.5 dBFS at 70 MHz (2.6 V p-p input span) SERIAL D1+A LVDS D1–A SFDR = 90 dBc (to Nyquist, 2.0 V p-p input span) VIN+B 16 PIPELINE DIGITAL SERIAL D0+B DNL = ±0.7 LSB; INL = ±3.5 LSB (2.0 V p-p input span) VIN–B ADC SERIALIZER LVDS D0–B RBIAS Serial LVDS (ANSI-644, default) and low power, reduced SERIAL D1+B VREF LVDS D1–B range option (similar to IEEE 1596.3) SENSE FCO+ REF 1V AD9653 650 MHz full power analog bandwidth FCO– SELECT AGND D0+C SERIAL 2 V p-p input voltage range (supports up to 2.6 V p-p) LVDS D0–C VIN+C 16 Serial port control PIPELINE DIGITAL D1+C SERIAL VIN–C ADC SERIALIZER LVDS D1–C Full chip and individual channel power-down modes SERIAL D0+D 16 Flexible bit orientation VIN+D DIGITAL LVDS D0–D PIPELINE VIN–D ADC SERIALIZER Built-in and custom digital test pattern generation SERIAL D1+D LVDS D1–D Multichip sync and clock divider SERIAL PORT CLOCK DCO+ VCM INTERFACE Programmable output clock and data alignment MANAGEMENT DCO– Standby mode B P C S K+ K– DT L L APPLICATIONS C SYN C C K/
001
IO/OLM D CL
10538-
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Figure 1.
High speed imaging Quadrature radio receivers Diversity radio receivers
as programmable output clock and data alignment and digital
Test equipment
test pattern generation. The available digital test patterns include
GENERAL DESCRIPTION
built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital interface (SPI). converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The AD9653 is available in a RoHS-compliant, 48-lead LFCSP. The product operates at a conversion rate of up to 125 MSPS It is specified over the industrial temperature range of −40°C to and is optimized for outstanding dynamic performance and low +85°C. power in applications where a smal package size is critical.
PRODUCT HIGHLIGHTS
The ADC requires a single 1.8 V power supply and LVPECL-/ 1. Small Footprint. CMOS-/LVDS-compatible sample rate clock for full performance Four ADCs are contained in a smal , space-saving package. operation. No external reference or driver components are 2. Low power of 164 mW/channel at 125 MSPS with scalable required for many applications. power options. The ADC automatically multiplies the sample rate clock for the 3. Pin compatible to the AD9253 14-bit quad and the AD9633 appropriate LVDS serial data rate. A data clock output (DCO) for 12-bit quad ADC. capturing data on the output and a frame clock output (FCO) 4. Ease of Use. for signaling a new output byte are provided. Individual channel A data clock output (DCO) operates at frequencies of up to power-down is supported and typical y consumes less than 2 mW 500 MHz and supports double data rate (DDR) operation. when al channels are disabled. The ADC contains several features 5. User Flexibility. designed to maximize flexibility and minimize system cost, such The SPI control offers a wide range of flexible features to meet specific system requirements.
Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.3 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x04, Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Clock (Register 0x09) Bits[7:1]—Open Bit 0—Duty Cycle Stabilize Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—1 Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Sample Rate Override (Register 0x100) User Input/Output Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User Input/Output Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT CROSSTALK PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE