Datasheet AD9645 (Analog Devices) - 4

Data Sheet AD9645 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 1. AD9645-80 AD9645-125 Parameter1 Temp Min Typ Max Min Typ Max Unit
RESOLUTION 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −0.6 −0.2 +0.1 −0.6 −0.2 +0.2 % FSR Offset Matching Full −0.2 +0.1 +0.4 −0.2 +0.1 +0.4 % FSR Gain Error Full −4.3 −1.0 +2.2 −5.1 −1.5 +2.3 % FSR Gain Matching Full 0.5 2.2 0.6 2.6 % FSR Differential Nonlinearity (DNL) Full −0.6 +1.3 −0.6 +1.3 LSB 25°C ±0.65 ±0.65 LSB Integral Nonlinearity (INL) Full −2.6 +2.8 −3.6 +3.4 LSB 25°C ±1.1 ±1.5 LSB TEMPERATURE DRIFT Offset Error Full 2.7 3.3 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.98 1.0 1.02 0.98 1.0 1.02 V Load Regulation at 1.0 mA (V = 1 V) 25°C 2 2 mV REF Input Resistance 25°C 7.5 7.5 kΩ INPUT-REFERRED NOISE V = 1.0 V 25°C 0.95 1.0 LSB rms REF ANALOG INPUTS Differential Input Voltage (V = 1 V) Full 2 2 V p-p REF Common-Mode Voltage Full 0.9 0.9 V Common-Mode Range 25°C 0.5 1.3 0.5 1.3 V Differential Input Resistance 25°C 5.2 5.2 kΩ Differential Input Capacitance 25°C 3.5 3.5 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V I 2 Full 56 61 78 83 mA AVDD I (ANSI-644 Mode)2 Full 48 50 57 60 mA DRVDD I (Reduced Range Mode)2 25°C 39 DRVDD 48 mA TOTAL POWER CONSUMPTION DC Input Full 178 191 227 244 mW Sine Wave Input (Two Channels; Includes Output Drivers in Full 187 200 243 257 mW ANSI-644 Mode) Sine Wave Input (Two Channels; Includes Output Drivers in 25°C 171 227 mW Reduced Range Mode) Power-Down 25°C 2 2 mW Standby3 Full 92 101 115 126 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured with a low input frequency, full-scale sine wave on both channels. 3 Can be controlled via the SPI. Rev. B | Page 3 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9645-80 AD9645-125 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE