Datasheet AD9645 (Analog Devices)

Dual, 14-Bit, 80 MSPS/125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter Data Sheet AD9645 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V supply operation AVDD AGND DRVDD Low power: 122 mW per channel at 125 MSPS with scalable AD9645 D0A+ power options 14 D0A– VINA+ SNR = 74 dBFS (to Nyquist) 14-BIT PIPELINE D1A+ VINA– ADC D1A– SFDR = 91 dBc at 70 MHz 14 RS D0B+ VCM DNL = ±0.65 LSB (typical); INL = ±1.5 LSB (typical) E R AND DDR V E D0B– Serial LVDS (ANSI-644, default) and low power, reduced 14 IZ VINB+ DRI D1B+ 14-BIT PIPELINE AL range option (similar to IEEE 1596.3) DS VINB– ADC RI D1B– E V L 650 MHz full power analog bandwidth 14 DCO+ , S L L DCO– 2 V p-p input voltage range P REFERENCE FCO+ Serial port control FCO– Full chip and individual channel power-down modes Flexible bit orientation SERIAL PORT 1 TO 8 INTERFACE CLOCK DIVIDER Built-in and custom digital test pattern generation Clock divider
001
Programmable output clock and data alignment SCLK/ SDIO/ CSB CLK+ CLK– DFS PDWN
10537-
Programmable output resolution
Figure 1.
Standby mode
The ADC automatically multiplies the sample rate clock for the
APPLICATIONS
appropriate LVDS serial data rate. A data clock output (DCO) for
Communications
capturing data on the output and a frame clock output (FCO) for
Diversity radio systems
signaling a new output byte are provided. Individual channel
Multimode digital receivers
power-down is supported; the AD9645 typically consumes less
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
than 2 mW in the full power-down state. The ADC provides
I/Q demodulation systems
several features designed to maximize flexibility and minimize
Smart antenna systems
system cost, such as programmable output clock and data align-
Broadband data applications
ment and digital test pattern generation. The available digital
Battery-powered instruments
test patterns include built-in deterministic and pseudorandom
Handheld scope meters
patterns, along with custom user-defined test patterns entered via
Portable medical imaging and ultrasound
the serial port interface (SPI).
Radar/LIDAR
The AD9645 is available in a RoHS-compliant, 32-lead LFCSP.
GENERAL DESCRIPTION
It is specified over the industrial temperature range of −40°C to +85°C. The AD9645 is a dual, 14-bit, 80 MSPS/125 MSPS analog-to- digital converter (ADC) with an on-chip sample-and-hold circuit
PRODUCT HIGHLIGHTS
designed for low cost, low power, small size, and ease of use. 1. Small Footprint. Two ADCs are contained in a small, space- The product operates at a conversion rate of up to 125 MSPS saving package. and is optimized for outstanding dynamic performance and low 2. Low Power. The AD9645 uses 122 mW/channel at 125 MSPS power in applications where a smal package size is critical. with scalable power options. The ADC requires a single 1.8 V power supply and LVPECL-/ 3. Pin Compatibility with the AD9635, a 12-Bit Dual ADC. CMOS-/LVDS-compatible sample rate clock for full performance 4. Ease of Use. A data clock output (DCO) operates at operation. No external reference or driver components are frequencies of up to 500 MHz and supports double data required for many applications. rate (DDR) operation. 5. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9645-80 AD9645-125 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE