Datasheet AD7173-8 (Analog Devices) - 6

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AD7173-8 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS Input High Voltage, V 1 INH 2 V ≤ IOVDD ≤ 2.3 V 0.65 × IOVDD V 2.3 V ≤ IOVDD ≤ 5.5 V 0.7 × IOVDD V Input Low Voltage, V 1 INL 2 V ≤ IOVDD ≤ 2.3 V 0.35 × IOVDD V 2.3 V ≤ IOVDD ≤ 5.5 V 0.7 V Hysteresis1 IOVDD > 2.7 V 0.08 0.25 V IOVDD < 2.7 V 0.04 0.2 V Leakage Currents −10 +10 µA LOGIC OUTPUT (DOUT/RDY) Output High Voltage, V 1 OH IOVDD ≥ 4.5 V, ISOURCE = 1 mA 0.8 × IOVDD V 2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 μA 0.8 × IOVDD V IOVDD < 2.7 V, ISOURCE = 200 μA 0.8 × IOVDD V Output Low Voltage, V 1 OL IOVDD ≥ 4.5 V, ISINK = 2 mA 0.4 V 2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA 0.4 V IOVDD < 2.7 V, ISINK = 400 μA 0.4 V Leakage Current Floating state −10 +10 µA Output Capacitance Floating state 10 pF SYSTEM CALIBRATION1 Full-Scale Calibration Limit 1.05 × FS V Zero-Scale Calibration Limit −1.05 × FS V Input Span 0.8 × FS 2.1 × FS V POWER REQUIREMENTS Power Supply Voltage AVDD1 − AVSS 3.0 5.5 V AVDD2 − AVSS 2 5.5 V AVSS − DGND −2.75 0 V IOVDD − DGND 2 5.5 V IOVDD − AVSS For AVSS < DGND 6.35 V POWER SUPPLY CURRENTS All outputs unloaded Full Operating Mode AVDD1 Current AVDD1 = 5 V Typical, AIN± and REF± buffers disabled; external 0.23 0.27 mA 5.5 V Maximum reference AIN± and REF± buffers disabled; internal 0.42 0.49 mA reference AIN± and REF± buffers enabled; external 2.12 2.71 mA reference Each enabled buffered pair: AIN+, AIN− and 0.945 1.22 mA REF+, REF− AVDD1 = 3.3 V Typical, AIN± and REF± buffers disabled; external 0.16 0.19 mA 3.6 V Maximum1 reference AIN± and REF± buffers disabled; internal 0.34 0.4 mA reference AIN± and REF± buffers enabled; external 1.9 2.45 mA reference Each enabled buffered pair: AIN+, AIN− and 0.87 1.13 mA REF+, REF− AVDD2 Current External reference 1 1.15 mA Internal reference 1.25 1.4 mA IOVDD Current External clock 0.24 0.39 mA Internal clock 0.52 0.76 mA External crystal 0.9 mA Standby Mode Standby (LDO on) Reference off, total current consumption 25 µA Reference on, total current consumption 400 µA Power-Down Mode Full power-down, LDO, REF± 2 10 µA Rev. B | Page 6 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES