Datasheet AD7173-8 (Analog Devices) - 5

link to page 4 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7
Data Sheet AD7173-8 Parameter Test Conditions/Comments Min Typ Max Unit
Power Supply Rejection AVDD1 and AVDD2 90 dB (Line Regulation) Load Regulation ∆VOUT/∆IL 140 ppm/mA Voltage Noise eN, 0.1 Hz to 10 Hz 6.5 µV rms Voltage Noise Density eN, 1 kHz 215 nV/√Hz Turn-On Settling Time 100 nF capacitor 60 µs Long-Term Stability3 1000 hours 460 ppm Short Circuit ISC 25 mA EXTERNAL REFERENCE Reference Input Voltage Reference input = (REF+) − (REF−) 1 2.5 AVDD1 V Absolute Reference Input Voltage Limits1 Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Buffers Enabled AVSS AVDD1 V Average Reference Input Current Buffers Disabled ±9 µA/V Buffers Enabled ±50 nA Average Reference Input Current Drift Buffers disabled External clock ±5 nA/V/°C Internal clock ±6 nA/V/°C Normal Mode Rejection1 See the Rejection parameter Common-Mode Rejection 83 dB TEMPERATURE SENSOR Accuracy After user calibration at 25°C ±2 °C Sensitivity 477 µV/°C BURNOUT CURRENTS Source/Sink Current Analog input buffers must be enabled ±10 µA BRIDGE POWER-DOWN SWITCH RON 24 Ω Allowable Currents 16 mA GENERAL-PURPOSE I/O (GPIO0, GPIO1, With respect to AVSS GPO2, GPO3) Input Mode Leakage Current1 −10 +10 µA Floating State Output Capacitance 5 pF AVDD1 − AVSS = 5 V Output High Voltage, V 1 OH ISOURCE = 200 µA AVSS + 4 V Output Low Voltage, V 1 OL ISINK = 800 µA AVSS + 0.4 V Input High Voltage, V 1 IH AVSS + 3 V Input Low Voltage, V 1 IL AVSS + 0.7 V AVDD1 − AVSS = 3.3 V Output High Voltage, V 1 OH ISOURCE = 200 µA AVSS + 2.7 V Output Low Voltage, V 1 OL ISINK = 800 µA AVSS + 0.27 V Input High Voltage, V 1 IH AVSS + 2 V Input Low Voltage, V 1 IL AVSS + 0.45 V CLOCK Internal Clock Frequency 2 MHz Accuracy −2.5 +2.5 % Duty Cycle 50:50 Output Low Voltage, VOL 0.4 V Output High Voltage, VOH 0.8 × IOVDD V Crystal Frequency 14 16 16.384 MHz Start-Up Time 10 µs External Clock (CLKIO) 2 2.048 MHz Duty Cycle1 Typical duty cycle 50:50 (maximum:minimum) 30:70 50:50 70:30 Rev. B | Page 5 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES