Datasheet AD9691 (Analog Devices) - 7

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AD9691 Data Sheet Parameter Temperature Min Typ Max Unit
LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY) Logic Compliance Full CMOS Logic 1 Voltage Full 0.8 × SPIVDD V Logic 0 Voltage Full 0 0.5 V Input Resistance Full 30 kΩ LOGIC OUTPUT (SDIO) Logic Compliance Full CMOS Logic 1 Voltage (IOH = 800 µA) Full 0.8 × SPIVDD V Logic 0 Voltage (IOL = 50 µA) Full 0 0.5 V SYNC INPUTS (SYNCINB+, SYNCINB−) Logic Compliance Full LVDS/LVPECL/CMOS Differential Input Voltage Full 400 1200 1800 mV p-p Input Common-Mode Voltage Full 0.6 0.85 2.0 V Input Resistance (Differential) Full 35 kΩ Input Capacitance Full 2.5 pF LOGIC OUTPUTS (FD_A, FD_B) Logic Compliance Full CMOS Logic 1 Voltage Full 0.8 × SPIVDD V Logic 0 Voltage Full 0 0.5 V Input Resistance Full 30 kΩ DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 7) Logic Compliance Full CML Differential Output Voltage Full 360 770 mV p-p Output Common-Mode Voltage (VCM), AC-Coupled 25°C 0 1.8 V Short-Circuit Current (IDSHORT) 25°C −100 +100 mA Differential Return Loss (RLDIFF)1 25°C 8 dB Common-Mode Return Loss (RLCM)1 25°C 6 dB Differential Termination Impedance Full 80 100 120 Ω 1 Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate.
SWITCHING SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p ful -scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 4. Parameter Temperature Min Typ Max Unit
CLOCK Clock Rate (at CLK+/CLK− Pins) Full 0.3 4 GHz Maximum Sample Rate1 Full 1250 MSPS Minimum Sample Rate2 Full 300 MSPS Clock Pulse Width High Full 400 ps Low Full 400 ps OUTPUT PARAMETERS Unit Interval (UI)3 Full 320 160 ps Rise Time (tR) (20% to 80% into 100 Ω Load) 25°C 24 32 ps Fall Time (tF) (20% to 80% into 100 Ω Load) 25°C 24 32 ps PLL Lock Time 25°C 2 ms Data Rate per Channel (NRZ)4 25°C 3.125 6.25 12.5 Gbps Rev. 0 | Page 6 of 72 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider ½ Period Delay Adjust Input Clock Divider Clock Fine Delay Adjust Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTERS (DDCS) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Two DDCs ) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 78) AND AGND (PIN 77 AND PIN 81) OUTLINE DIMENSIONS ORDERING GUIDE