Datasheet AD9691 (Analog Devices) - 10

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Data Sheet AD9691 ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS Parameter Rating
Typical θJA, ΨJB, θJC_TOP, and θJC_BOT values are specified vs. the Electrical number of printed circuit board (PCB) layers in different AVDD1 to AGND 1.32 V airflow velocities (in m/sec). Airflow increases heat dissipation AVDD1_SR to AGND 1.32 V effectively reducing θJA and ΨJB. The use of appropriate thermal AVDD2 to AGND 2.75 V management techniques is recommended to ensure that the AVDD3 to AGND 3.63 V maximum junction temperature does not exceed the limits shown DVDD to DGND 1.32 V in Table 7. DRVDD to DRGND 1.32 V
Table 7.
SPIVDD to AGND 3.63 V AGND to DRGND −0.3 V to +0.3 V
Airflow PCB Velocity
VIN±x to AGND 3.2 V
Type (m/sec) θ 1, 2 1, 3 1, 4 1, 4 JA ΨJB θJC_TOP θJC_BOT Unit
SCLK, SDIO, CSB to AGND −0.3 V to SPIVDD + 0.3 V JEDEC 0.0 17.41 4.70 6.01 1.12 °C/W PDWN/STBY to AGND −0.3 V to SPIVDD + 0.3 V 2s2p 1.0 13.83 4.32 N/A5 N/A5 °C/W Environmental Board 2.5 12.47 4.21 N/A5 N/A5 °C/W Operating Temperature Range −40°C to +85°C 1 Maximum Junction Temperature 115°C Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Storage Temperature Range −65°C to +150°C 3 Per JEDEC JESD51-8 (still air). (Ambient) 4 Per MIL-STD 883, Method 1012.1. 5 N/A means not applicable. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these
ESD CAUTION
or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 9 of 72 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider ½ Period Delay Adjust Input Clock Divider Clock Fine Delay Adjust Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTERS (DDCS) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Two DDCs ) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 78) AND AGND (PIN 77 AND PIN 81) OUTLINE DIMENSIONS ORDERING GUIDE