Datasheet AD9691 (Analog Devices) - 4

Data Sheet AD9691 SPECIFICATIONS DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p ful -scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 1. Parameter Temperature Min Typ Max Unit
RESOLUTION Full 14 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full −0.31 0 +0.31 % FSR Offset Matching Full 0 0.3 % FSR Gain Error Full −6 0 +6 % FSR Gain Matching Full 1 3.9 % FSR Differential Nonlinearity (DNL) Full −0.8 ±0.5 +0.8 LSB Integral Nonlinearity (INL) Full −6.5 ±2.6 +6.5 LSB TEMPERATURE DRIFT Offset Error 25°C −26 ppm/°C Gain Error 25°C ±9.8 ppm/°C INTERNAL VOLTAGE REFERENCE Voltage Full 1.0 V INPUT REFERRED NOISE VREF = 1.0 V 25°C 3.53 LSB rms ANALOG INPUTS Differential Input Voltage Range Full 1.58 V p-p Common-Mode Voltage (VCM) 25°C 2.05 V Differential Input Capacitance 25°C 1.5 pF Analog Input Full Power Bandwidth 25°C 2 GHz POWER SUPPLY AVDD1 Full 1.22 1.25 1.28 V AVDD2 Full 2.44 2.50 2.56 V AVDD3 Full 3.2 3.3 3.4 V AVDD1_SR Full 1.22 1.25 1.28 V DVDD Full 1.22 1.25 1.28 V DRVDD Full 1.22 1.25 1.28 V SPIVDD Full 1.7 1.8 3.4 V IAVDD1 Full 800 840 mA IAVDD2 Full 670 770 mA IAVDD3 Full 125 140 mA IAVDD1_SR Full 15 18 mA I 1 DVDD Full 250 290 mA I 2 DRVDD Full 310 380 mA ISPIVDD Full 5 6 mA POWER CONSUMPTION Total Power Dissipation (Including Output Drivers)1 Full 3.8 W Power-Down Dissipation Full 0.9 mW Standby3 Full 1.5 W 1 Default mode. No DDCs used. L = 8, M = 2, and F = 1. 2 All lanes running. Power dissipation on DRVDD changes with the lane rate and number of lanes used. 3 Standby mode can be control ed by the SPI. Rev. 0 | Page 3 of 72 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider ½ Period Delay Adjust Input Clock Divider Clock Fine Delay Adjust Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTERS (DDCS) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Two DDCs ) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 78) AND AGND (PIN 77 AND PIN 81) OUTLINE DIMENSIONS ORDERING GUIDE