Datasheet AD7768, AD7768-4 (Analog Devices) - 7

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Data Sheet AD7768/AD7768-4 Parameter Test Conditions/Comments Min Typ Max Unit
ACCURACY See Table 2 for 1.8 V operation INL Endpoint method ±2 ±7 ppm of FSR Offset Error4 DCLK frequency ≤ 24 MHz ±50 ±115 µV 24 MHz to 32.768 MHz DCLK frequency2 ±75 ±150 µV Offset Error Drift DCLK frequency ≤ 24 MHz ±250 nV/°C 24 MHz to 32.768 MHz DCLK frequency ±750 nV/°C Gain Error4 TA = 25°C ±30 ±70 ppm of FSR Gain Drift vs. Temperature2 ±0.5 ±1 ppm/°C VCM PIN Output With respect to AVSS (AVDD1 − V AVSS)/2 Load Regulation (∆VOUT/∆IL) 400 µV/mA Voltage Regulation Applies to the following VCM output 5 µV/V options only: VCM = ∆VOUT/∆(AVDD1 − AVSS)/2; VCM = 1.65 V; and VCM = 2.5 V Short-Circuit Current 30 mA ANALOG INPUTS See the Analog Inputs section Differential Input Voltage Range VREF = (REFx+) − (REFx−) −VREF +VREF V Input Common-Mode Range2 AVSS AVDD1 V Absolute Analog Input AVSS AVDD1 V Voltage Limits2 Analog Input Current Fast mode Unbuffered Differential component ±48 µA/V Common-mode component ±17 µA/V Precharge Buffer On5 −20 µA Input Current Drift Fast mode; see Figure 62 Unbuffered ±5 nA/V/°C Precharge Buffer On ±31 nA/°C EXTERNAL REFERENCE Reference Voltage VREF = (REFx+) − (REFx−) 1 AVDD1 − AVSS V Absolute Reference Voltage Reference precharge buffers off AVSS − 0.05 AVDD1 + 0.05 V Limits2 Reference precharge buffer on AVSS AVDD1 V Average Reference Current Fast mode; see Figure 63 Reference precharge buffers off ±72 µA/V/channel Reference precharge buffers on ±16 µA/V/channel Average Reference Current Drift Fast mode; see Figure 63 Reference precharge buffers off ±1.7 nA/V/°C Reference precharge buffers on ±49 nA/V/°C Common-Mode Rejection 95 dB DIGITAL FILTER RESPONSE Low Ripple Wideband Filter FILTER = 0 Decimation Rate Up to six selectable decimation rates; see 32 1024 the Decimation Rate Control section Group Delay Latency 34/ODR sec Settling Time Complete settling, see Table 35 68/ODR sec Pass-Band Ripple2 From dc to 102.4 kHz at 256 kSPS ±0.005 dB Pass Band ±0.005 dB bandwidth 0.4 × ODR Hz −0.1 dB bandwidth 0.409 × ODR Hz −3 dB bandwidth 0.433 × ODR Hz Stop Band Frequency Attenuation > 105 dB 0.499 × ODR Hz Stop Band Attenuation See the Wideband Low Ripple Filter section 105 dB Rev. A | Page 7 of 99 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 1.8 V IOVDD SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA Chip Error Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface FUNCTIONALITY GPIO FUNCTIONALITY AD7768 REGISTER MAP DETAILS (SPI CONTROL) AD7768 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER AD7768-4 REGISTER MAP DETAILS (SPI CONTROL) AD7768-4 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE