Datasheet AD7768, AD7768-4 (Analog Devices) - 3
| Hersteller | Analog Devices |
| Beschreibung | 4-Channel, 24-Bit, Simultaneous Sampling ADC, Power Scaling, 110.8 kHz BW |
| Seiten / Seite | 99 / 3 — Data Sheet. AD7768/AD7768-4. REVISION HISTORY 3/16—Rev. 0 to Rev. A |
| Revision | B |
| Dateiformat / Größe | PDF / 2.4 Mb |
| Dokumentensprache | Englisch |
Data Sheet. AD7768/AD7768-4. REVISION HISTORY 3/16—Rev. 0 to Rev. A
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Data Sheet AD7768/AD7768-4
Digital Filter RAM Built In Self Test (BIST) Register .. 92 Negative Reference Precharge Buffer Enable Register ... 95 Status Register .. 92 Offset Registers .. 96 Revision Identification Register .. 93 Gain Registers .. 96 GPIO Control Register ... 93 Sync Phase Offset Registers ... 96 GPIO Write Data Register ... 94 ADC Diagnostic Receive Select Register ... 96 GPIO Read Data Register .. 94 ADC Diagnostic Control Register .. 97 Analog Input Precharge Buffer Enable Register Channel 0 Modulator Delay Control Register ... 97 And Channel 1 ... 94 Chopping Control Register .. 98 Analog Input Precharge Buffer Enable Register Channel 2 Outline Dimensions .. 99 And Channel 3 ... 95 Ordering Guide ... 99 Positive Reference Precharge Buffer Enable Register ... 95
REVISION HISTORY 3/16—Rev. 0 to Rev. A
Changes to RAM Built In Self Test Section ... 53 Added AD7768-4 ... Universal Changes to Analog Inputs Section and Figure 85 ... 55 Changed Precharge Analog Input Reference to Analog Input Added Figure 86 .. 55 Precharge .. Throughout Added Table 27 .. 56 Changes to General Description Section ... 5 Changes to VCM Section, Reference Input Section, and Digital Changes to Table 1 .. 6 Filtering Section .. 56 Changes to Table 2 .. 12 Changes to Figure 87, Figure 88, and Figure 89 .. 57 Changes to Table 3 and t30 Parameter, Table 4 ... 16 Changes to Antialiasing Section and Modulator Sampling Changes to Table 5 .. 17 Frequency Section ... 58 Changes to t30 Parameter, Table 6 and Figure 2 ... 18 Changes to Modulator Chopping Frequency Section and Changes to Figure 4 and Figure 7 .. 19 Table 29, and Modulator Saturation Point Section, .. 59 Changes to Figure 8 and Figure 9 .. 20 Changes to Sync Phase Offset Adjustment Section .. 60 Changes to Figure 10 and Table 9 ... 22 Changes to Setting the Format of Data Output Section .. 61 Added Figure 11 and Table 10; Renumbered Sequentially .. 26 Added Table 32 and Figure 93 ... 61 Changes to Typical Performance Characteristics Section ... 30 Changes to Figure 94 Caption and ADC Conversion Output: Changes to Theory of Operation Section and Clocking, Header and Data Section ... 62 Sampling Tree, and Power Scaling Section .. 41 Changes to Data Interface: Standard Conversion Operation Changes to Table 11 .. 42 Section .. 63 Added Example of Power vs. Noise Performance Optimization Changes to Figure 99 .. 64 Section and Clocking Out the ADC Conversion Results Added Figure 100 .. 64 (DCLK) Section ... 42 Added Figure 101 .. 65 Changes to Applications Information Section and Figure 73 ... 44 Changes to Daisy-Chaining Section and Figure 104 .. 66 Changes to Table 14 and Power Supplies Section ... 45 Added Figure 105 .. 67 Moved 1.8 V IOVDD Operation Section ... 46 Changes to CRC Check on Data Interface Section .. 68 Changes to Figure 75, Analog Supply Internal Connectivity Changes to Table 35 .. 69 Section, and Pin Control Section .. 46 Changes to Table 36 .. 70 Added Figure 76 .. 47 Changes to GPIO Functionality Section and Figure 108 ... 71 Changes to Channel Standby Section and Accessing the ADC Added Figure 109 .. 71 Register Map Section .. 49 Changes to AD7768 Register Map Details (SPI Control) Section Added Table 22 .. 49 and Table 37 ... 72 Changes to Channel Configuration Section .. 50 Changes to Channel Standby Register Section ... 74 Changes to Channel Modes Section, Reset over SPI Control Changes to Table 42 and Table 43 ... 76 Interface Section, Sleep Mode Section, and Channel Standby Changes to Table 44 .. 77 Section .. 51 Changes to Table 45 and Table 46 ... 78 Changes to MCLK Source Selection Section, Interface Changes to Table 49 .. 79 Configuration Section, and ADC Synchronization over SPI Changes to Table 61 .. 85 Section .. 52 Added AD7768-4 Register Map Details (SPI Control) Section and Added Figure 81 .. 52 Table 63 .. 86 Rev. A | Page 3 of 99 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 1.8 V IOVDD SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA Chip Error Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface FUNCTIONALITY GPIO FUNCTIONALITY AD7768 REGISTER MAP DETAILS (SPI CONTROL) AD7768 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER AD7768-4 REGISTER MAP DETAILS (SPI CONTROL) AD7768-4 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7768/AD7768-4
Digital Filter RAM Built In Self Test (BIST) Register .. 92 Negative Reference Precharge Buffer Enable Register ... 95 Status Register .. 92 Offset Registers .. 96 Revision Identification Register .. 93 Gain Registers .. 96 GPIO Control Register ... 93 Sync Phase Offset Registers ... 96 GPIO Write Data Register ... 94 ADC Diagnostic Receive Select Register ... 96 GPIO Read Data Register .. 94 ADC Diagnostic Control Register .. 97 Analog Input Precharge Buffer Enable Register Channel 0 Modulator Delay Control Register ... 97 And Channel 1 ... 94 Chopping Control Register .. 98 Analog Input Precharge Buffer Enable Register Channel 2 Outline Dimensions .. 99 And Channel 3 ... 95 Ordering Guide ... 99 Positive Reference Precharge Buffer Enable Register ... 95
REVISION HISTORY 3/16—Rev. 0 to Rev. A
Changes to RAM Built In Self Test Section ... 53 Added AD7768-4 ... Universal Changes to Analog Inputs Section and Figure 85 ... 55 Changed Precharge Analog Input Reference to Analog Input Added Figure 86 .. 55 Precharge .. Throughout Added Table 27 .. 56 Changes to General Description Section ... 5 Changes to VCM Section, Reference Input Section, and Digital Changes to Table 1 .. 6 Filtering Section .. 56 Changes to Table 2 .. 12 Changes to Figure 87, Figure 88, and Figure 89 .. 57 Changes to Table 3 and t30 Parameter, Table 4 ... 16 Changes to Antialiasing Section and Modulator Sampling Changes to Table 5 .. 17 Frequency Section ... 58 Changes to t30 Parameter, Table 6 and Figure 2 ... 18 Changes to Modulator Chopping Frequency Section and Changes to Figure 4 and Figure 7 .. 19 Table 29, and Modulator Saturation Point Section, .. 59 Changes to Figure 8 and Figure 9 .. 20 Changes to Sync Phase Offset Adjustment Section .. 60 Changes to Figure 10 and Table 9 ... 22 Changes to Setting the Format of Data Output Section .. 61 Added Figure 11 and Table 10; Renumbered Sequentially .. 26 Added Table 32 and Figure 93 ... 61 Changes to Typical Performance Characteristics Section ... 30 Changes to Figure 94 Caption and ADC Conversion Output: Changes to Theory of Operation Section and Clocking, Header and Data Section ... 62 Sampling Tree, and Power Scaling Section .. 41 Changes to Data Interface: Standard Conversion Operation Changes to Table 11 .. 42 Section .. 63 Added Example of Power vs. Noise Performance Optimization Changes to Figure 99 .. 64 Section and Clocking Out the ADC Conversion Results Added Figure 100 .. 64 (DCLK) Section ... 42 Added Figure 101 .. 65 Changes to Applications Information Section and Figure 73 ... 44 Changes to Daisy-Chaining Section and Figure 104 .. 66 Changes to Table 14 and Power Supplies Section ... 45 Added Figure 105 .. 67 Moved 1.8 V IOVDD Operation Section ... 46 Changes to CRC Check on Data Interface Section .. 68 Changes to Figure 75, Analog Supply Internal Connectivity Changes to Table 35 .. 69 Section, and Pin Control Section .. 46 Changes to Table 36 .. 70 Added Figure 76 .. 47 Changes to GPIO Functionality Section and Figure 108 ... 71 Changes to Channel Standby Section and Accessing the ADC Added Figure 109 .. 71 Register Map Section .. 49 Changes to AD7768 Register Map Details (SPI Control) Section Added Table 22 .. 49 and Table 37 ... 72 Changes to Channel Configuration Section .. 50 Changes to Channel Standby Register Section ... 74 Changes to Channel Modes Section, Reset over SPI Control Changes to Table 42 and Table 43 ... 76 Interface Section, Sleep Mode Section, and Channel Standby Changes to Table 44 .. 77 Section .. 51 Changes to Table 45 and Table 46 ... 78 Changes to MCLK Source Selection Section, Interface Changes to Table 49 .. 79 Configuration Section, and ADC Synchronization over SPI Changes to Table 61 .. 85 Section .. 52 Added AD7768-4 Register Map Details (SPI Control) Section and Added Figure 81 .. 52 Table 63 .. 86 Rev. A | Page 3 of 99 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 1.8 V IOVDD SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA Chip Error Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface FUNCTIONALITY GPIO FUNCTIONALITY AD7768 REGISTER MAP DETAILS (SPI CONTROL) AD7768 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER AD7768-4 REGISTER MAP DETAILS (SPI CONTROL) AD7768-4 REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 AND CHANNEL 1 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 2 AND CHANNEL 3 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE