Datasheet AD9208 (Analog Devices) - 5

AD9208 Data Sheet GENERAL DESCRIPTION
The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter capability. The signal monitoring block provides additional (ADC). The device has an on-chip buffer and a sample-and- information about the signal being digitized by the ADC. hold circuit designed for low power, small size, and ease of use. The user can configure the Subclasss 1 JESD204B-based high This product is designed to support communications applications speed serialized output in a variety of one-lane, two-lane, four- capable of direct sampling wide bandwidth analog signals of up lane, and eight-lane configurations, depending on the DDC to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. configuration and the acceptable lane rate of the receiving logic The AD9208 is optimized for wide input bandwidth, high sampling device. Multidevice synchronization is supported through the rate, excellent linearity, and low power in a small package. SYSREF± and SYNCINB± input pins. The dual ADC cores feature a multistage, differential pipelined The AD9208 has flexible power-down options that allow architecture with integrated output error correction logic. Each significant power savings when desired. All of these features can ADC features wide bandwidth inputs supporting a variety of be programmed using a 3-wire serial port interface (SPI). user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals The AD9208 is available in a Pb-free, 196-ball BGA, specified are differential inputs. The ADC data outputs are internally over the −40°C to +85°C ambient temperature range. This connected to four digital downconverters (DDCs) through a product is protected by a U.S. patent. crossbar mux. Each DDC consists of up to five cascaded signal Note that throughout this data sheet, multifunction pins, such processing stages: a 48-bit frequency translator (numerically as FD_A/GPIO_A0, are referred to either by the entire pin controlled oscillator (NCO)), and up to four half-band decimation name or by a single function of the pin, for example, FD_A, filters. The NCO has the option to select preset bands over the when only that function is relevant. general-purpose input/output (GPIO) pins, which enables the
PRODUCT HIGHLIGHTS
selection of up to three bands. Operation of the AD9208 between the DDC modes is selectable via SPI-programmable profiles. 1. Wide, input −3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. In addition to the DDC blocks, the AD9208 has several functions 2. Four integrated, wideband decimation filter and NCO that simplify the automatic gain control (AGC) function in a blocks supporting multiband receivers. communications receiver. The programmable threshold detector 3. Fast NCO switching enabled through the GPIO pins. allows monitoring of the incoming signal power using the fast 4. A SPI controls various product features and functions to detect control bits in Register 0x0245 of the ADC. If the input meet specific system requirements. signal level exceeds the programmable threshold, the fast detect 5. Programmable fast overrange detection and signal indicator goes high. Because this threshold indicator has low monitoring. latency, the user can quickly turn down the system gain to avoid 6. On-chip temperature diode for system thermal management. an overrange condition at the ADC input. In addition to the fast 7. 12 mm × 12 mm, 196-ball BGA. detect outputs, the AD9208 also offers signal monitoring Rev. 0 | Page 4 of 136 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Dither Absolute Maximum Input Swing VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay and Superfine Delay Adjust Clock Coupling Considerations Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING PROGRAMMABLE FIR FILTERS SUPPORTED MODES PROGRAMMING INSTRUCTIONS DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION DDC Frequency Translation Stage (Optional) DDC Filtering Stage DDC Gain Stage (Optional) DDC Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION DDC Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode NCO FTW/POW/MAW/MAB Coherent Mode NCO Channel Selection Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization For these reasons, the AD9208 contains a synchronization triggering mechanism that allows the following: NCO Multichip Synchronization at Startup NCO Multichip Synchronization During Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS HB4 Filter Description HB3 Filter Description HB2 Filter Description HB1 Filter Description TB2 Filter Description TB1 Filter Description FB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC MIXED DECIMATION SETTINGS DDC EXAMPLE CONFIGURATIONS DDC POWER CONSUMPTION SIGNAL MONITOR SPORT OVER JESD204B DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) fS × 4 MODE SETTING UP THE AD9208 DIGITAL INTERFACE Example 1—Full Bandwidth Mode Example 2—ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF INPUT SYSREF Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS LMFC REFERENCED LATENCY TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTER DETAILS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS LAYOUT GUIDELINES AVDD1_SR (PIN E7) AND AGND (PIN E6 AND PIN E8) OUTLINE DIMENSIONS ORDERING GUIDE