Datasheet AD9208 (Analog Devices)

14-Bit, 3 GSPS, JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9208 FEATURES 2 integrated, wideband digital processors per channel JESD204B (Subclass 1) coded serial digital outputs 48-bit NCO Support for lane rates up to 16 Gbps per lane 4 cascaded half-band filters 1.65 W total power per channel at 3 GSPS (default settings) Phase coherent NCO switching Performance at −2 dBFS amplitude, 2.6 GHz input Up to 4 channels available SFDR = 70 dBFS Serial port control SNR = 57.2 dBFS Integer clock with divide by 2 and divide by 4 options Performance at −9 dBFS amplitude, 2.6 GHz input Flexible JESD204B lane configurations SFDR = 78 dBFS On-chip dither SNR = 59.5 dBFS APPLICATIONS Integrated input buffer Diversity multiband and multimode digital receivers Noise density = −152 dBFS/Hz 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A 0.975 V, 1.9 V, and 2.5 V dc supply operation Electronic test and measurement systems 9 GHz analog input full power bandwidth (−3 dB) Phased array radar and electronic warfare Amplitude detect bits for efficient AGC implementation DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD1 DRVDD2 SPIVDD (0.975V) (1.9V) (2.5V) (0.975V) (0.975V) (0.975V) (1.9V) (1.9V) BUFFER VIN+A ADC 14 VIN–A CORE E UX DIGITAL DOWN- UX SERDOUT0± R CONVERTER ABL E SERDOUT1± M JESD204B 8 SERDOUT2± FAST SIGNAL LT LINK DETECT MONITOR BAR M BAR M SERDOUT3± AND RAM FI S S S S Tx SERDOUT4± G FIR DIGITAL DOWN- OUTPUTS SERDOUT5± RO CRO CONVERTER CRO P SERDOUT6± VIN+B 14 ADC SERDOUT7± VIN–B CORE BUFFER VREF SYNCINB± PDWN/STBY JESD204B CLOCK SYSREF± SUBCLASS 1 FD_A/GPIO_A0 CONTROL DISTRIBUTION GPIO_A1 CLK+ GPIO MUX FD_B/GPIO_B0 SPI AND CONTROL GPIO_B1 REGISTERS CLK– ÷2 ÷4 AD9208
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AGND SDIO SCLK CSB DRGND DGND
155 Figure 1.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Dither Absolute Maximum Input Swing VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay and Superfine Delay Adjust Clock Coupling Considerations Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING PROGRAMMABLE FIR FILTERS SUPPORTED MODES PROGRAMMING INSTRUCTIONS DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION DDC Frequency Translation Stage (Optional) DDC Filtering Stage DDC Gain Stage (Optional) DDC Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION DDC Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode NCO FTW/POW/MAW/MAB Coherent Mode NCO Channel Selection Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization For these reasons, the AD9208 contains a synchronization triggering mechanism that allows the following: NCO Multichip Synchronization at Startup NCO Multichip Synchronization During Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS HB4 Filter Description HB3 Filter Description HB2 Filter Description HB1 Filter Description TB2 Filter Description TB1 Filter Description FB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC MIXED DECIMATION SETTINGS DDC EXAMPLE CONFIGURATIONS DDC POWER CONSUMPTION SIGNAL MONITOR SPORT OVER JESD204B DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) fS × 4 MODE SETTING UP THE AD9208 DIGITAL INTERFACE Example 1—Full Bandwidth Mode Example 2—ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF INPUT SYSREF Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS LMFC REFERENCED LATENCY TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTER DETAILS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS LAYOUT GUIDELINES AVDD1_SR (PIN E7) AND AGND (PIN E6 AND PIN E8) OUTLINE DIMENSIONS ORDERING GUIDE