Datasheet LT8415 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Ultralow Power Boost Converter with Dual Half-Bridge Switches |
| Seiten / Seite | 14 / 10 — APPLICATIONS INFORMATION. Board Layout Considerations. SHDN Pin … |
| Dateiformat / Größe | PDF / 268 Kb |
| Dokumentensprache | Englisch |
APPLICATIONS INFORMATION. Board Layout Considerations. SHDN Pin Comparator and Hysteresis Current
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LT8415
APPLICATIONS INFORMATION
If the application doesn’t require the output disconnect
Board Layout Considerations
function, the CAP and VOUT pin can be shorted, and higher As with all switching regulators, careful attention must power converter efficiency can be achieved. be paid to the PCB layout and component placement. To
SHDN Pin Comparator and Hysteresis Current
maximize efficiency, switch rise and fall times are made as short as possible. To prevent electromagnetic interfer- An internal comparator compares the SHDN pin voltage ence (EMI) problems, proper layout of the high frequency with an internal voltage reference (~1.3V) which gives a switching path is essential. The voltage signal of the SW pin precise turn-on voltage level. The internal hysteresis of this has sharp rising and falling edges. Minimize the length and turn-on voltage is about 60mV. When the chip is turned on, area of all traces connected to the SW pin and always use and the SHDN pin voltage is close to this turn-on voltage, a ground plane under the switching regulator to minimize 0.1μA current flows out of the SHDN pin. This current is interplane coupling. In addition, the FBP pin and VREF pin called SHDN pin hysteresis current, and will go away when are sensitive to noise. Minimizing the length and area of all the chip is off. By connecting the external resistors as in traces to these two pins is recommended. Recommended Figure 2, a user-programmable enable voltage function component placement is shown in Figure 3. can be realized. VIN SHDN The turn-on voltage for the configuration is: 1.30 • (1 + R1/R2) and the turn-off voltage is: SHDN FBP GND (1.24 – R3 V V • 10–7) • (1 + R1/R2) – R1 • 10–7 CC REF where R1, R2 and R3 are resistance value in Ω. GND CAP SW VOUT ENABLE VOLTAGE IN1 OUT1 R1 IN2 OUT2 R3 CONNECT TO SHDN PIN 8410 F03 R2 IN2 IN1 OUT1 OUT2 VIAS TO GROUND PLANE REQUIRED TO IMPROVE THERMAL PERFORMANCE
Figure 2. Programming Enable Voltage by Using External
VIAS FOR CAP AND VOUT GROUND RETURN THROUGH
Resistors
SECOND METAL LAYER, CAPACITOR GROUNDS MUST BE RETURNED DIRECTLY TO IC GROUND
Figure 3. Recommended Board Layout Half-Bridge Control Signals
The half-bridge is controlled by the IN1 and IN2 pins. The IN1 and IN2 pins should be driven with a logic signal. When the chip is enabled, the OUT1 and OUT2 voltages are equal to VOUT IN1 and IN2 are driven higher than 1V, and they are near GND when IN1 and IN2 are driven below 0.3V. Do not drive the IN1 or IN2 pins between 0.3V to 1V for more than 20µs since this will leave OUT1 or OUT2 in an uncertain state and may also cause shoot-through current. 8415fb 10 For more information www.linear.com/LT8415
APPLICATIONS INFORMATION
If the application doesn’t require the output disconnect
Board Layout Considerations
function, the CAP and VOUT pin can be shorted, and higher As with all switching regulators, careful attention must power converter efficiency can be achieved. be paid to the PCB layout and component placement. To
SHDN Pin Comparator and Hysteresis Current
maximize efficiency, switch rise and fall times are made as short as possible. To prevent electromagnetic interfer- An internal comparator compares the SHDN pin voltage ence (EMI) problems, proper layout of the high frequency with an internal voltage reference (~1.3V) which gives a switching path is essential. The voltage signal of the SW pin precise turn-on voltage level. The internal hysteresis of this has sharp rising and falling edges. Minimize the length and turn-on voltage is about 60mV. When the chip is turned on, area of all traces connected to the SW pin and always use and the SHDN pin voltage is close to this turn-on voltage, a ground plane under the switching regulator to minimize 0.1μA current flows out of the SHDN pin. This current is interplane coupling. In addition, the FBP pin and VREF pin called SHDN pin hysteresis current, and will go away when are sensitive to noise. Minimizing the length and area of all the chip is off. By connecting the external resistors as in traces to these two pins is recommended. Recommended Figure 2, a user-programmable enable voltage function component placement is shown in Figure 3. can be realized. VIN SHDN The turn-on voltage for the configuration is: 1.30 • (1 + R1/R2) and the turn-off voltage is: SHDN FBP GND (1.24 – R3 V V • 10–7) • (1 + R1/R2) – R1 • 10–7 CC REF where R1, R2 and R3 are resistance value in Ω. GND CAP SW VOUT ENABLE VOLTAGE IN1 OUT1 R1 IN2 OUT2 R3 CONNECT TO SHDN PIN 8410 F03 R2 IN2 IN1 OUT1 OUT2 VIAS TO GROUND PLANE REQUIRED TO IMPROVE THERMAL PERFORMANCE
Figure 2. Programming Enable Voltage by Using External
VIAS FOR CAP AND VOUT GROUND RETURN THROUGH
Resistors
SECOND METAL LAYER, CAPACITOR GROUNDS MUST BE RETURNED DIRECTLY TO IC GROUND
Figure 3. Recommended Board Layout Half-Bridge Control Signals
The half-bridge is controlled by the IN1 and IN2 pins. The IN1 and IN2 pins should be driven with a logic signal. When the chip is enabled, the OUT1 and OUT2 voltages are equal to VOUT IN1 and IN2 are driven higher than 1V, and they are near GND when IN1 and IN2 are driven below 0.3V. Do not drive the IN1 or IN2 pins between 0.3V to 1V for more than 20µs since this will leave OUT1 or OUT2 in an uncertain state and may also cause shoot-through current. 8415fb 10 For more information www.linear.com/LT8415