Datasheet LTC2472 (Analog Devices) - 8

LTC2470/LTC2472
applicaTions inForMaTion
complete, the SLEEP state is entered and power is reduced from MSB to LSB. The user can reliably latch this data to 2μA (maximum). The reference is powered up once CS on every rising edge of the external serial clock signal is brought low. The reference startup time is 12ms (if the driving the SCK pin. reference and compensation capacitor values are both During the DATA INPUT/OUTPUT state, the LTC2470/ 0.1μF). As the reference and compensation capacitors are LTC2472 can be programmed to SLEEP or NAP (default) decreased, the startup time is reduced (see Figure 3), but and the output rate can be updated. Data is shifted into the transition noise increases (see Figure 4). the device through the SDI pin on the rising edge of SCK. Upon entering the DATA INPUT/OUTPUT state, SDO The input word is 4 bits. If the first bit EN1 = 1 and the outputs the sign (D15) of the conversion result. During second bit EN2 = 0 the device is enabled for programming. this state, the ADC shifts the conversion result serially The following two bits (SPD and SLP) will be written into through the SDO output pin under the control of the SCK the device. SPD is used to select the output rate. If SPD = input pin. There is no latency in generating this data and 0 (Default) the output rate is 208sps and SPD = 1 sets a the result corresponds to the last completed conversion. 833sps output rate. The next bit (SLP) enables the sleep A new bit of data appears at the SDO pin following each or nap mode. If SLP = 0 (default) the reference remains falling edge detected at the SCK input pin and appears powered up at the end of each conversion cycle. If SLP = 1, the reference powers down following the next conver- 250 sion cycle. The remaining 12 SDI input bits are ignored (don’t care). 200 VCC = 2.7V SDI may also be tied directly to GND or VDD in order to 150 simplify the user interface. If SDI is tied LOW the output VCC = 4.1V 100 rate is 208sps and if SDI is tied HIGH the output rate is TIME (ms) 833sps. The reference sleep mode is disabled if SDI is 50 tied to GND or VDD. 0 VCC = 5.5V The DATA INPUT/OUTPUT state concludes in one of two different ways. First, the DATA INPUT/OUTPUT state opera- –50 1 0.1 0.01 0.001 tion is completed once all 16 data bits have been shifted CAPACITANCE (µF) 24702 F03 out and the clock then goes low. This corresponds to the 16th falling edge of SCK. Second, the DATA INPUT/OUT-
Figure 3. Reference Start-Up Time vs VREF and Compensation Capacitance
PUT state can be aborted at any time by a LOW-to-HIGH transition on the CS input. Following either one of these 25 two actions, the LTC2470/LTC2472 will enter the CONVERT state and initiate a new conversion cycle. 20 V RMS)
Power-Up Sequence
15 When the power supply voltage (VCC) applied to the con- 10 verter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of TRANSITION NOISE (µ 5 the conversion result. 0 When VCC rises above this critical threshold, the converter 0.0001 0.001 0.01 0.1 1 10 generates an internal power-on reset (POR) signal for CAPACITANCE (µF) 24702 F04 approximately 0.5ms. For proper operation VDD needs
Figure 4. Transition Noise RMS vs COMP and
to be restored to normal operating range (2.7V to 5.5V)
Reference Capacitance
24702fb 8 For more information www.linear.com/LTC2470 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs Power Requirements Digital Inputs and Digital Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts