Datasheet LTC2472 (Analog Devices) - 9

HerstellerAnalog Devices
BeschreibungSelectable 208sps/833sps, 16-Bit ΔΣ ADCs with 10ppm/°C Max Precision Reference
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applicaTions inForMaTion. Input Voltage Range (LTC2470). Input Voltage Range (LTC2472). Output Data Format. Ease of Use

applicaTions inForMaTion Input Voltage Range (LTC2470) Input Voltage Range (LTC2472) Output Data Format Ease of Use

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LTC2470/LTC2472
applicaTions inForMaTion
before the conclusion of the POR cycle. The POR signal
Input Voltage Range (LTC2470)
clears all internal registers. Following the POR signal, the Ignoring offset and full-scale errors, the LTC2470 will LTC2470/LTC2472 start a conversion cycle and follow the theoretically output an “all zero” digital result when the succession of states shown in Figure 2. The reference input is at ground (a zero scale input) and an “all one” startup time following a POR is 12ms (CCOMP = CREFOUT = digital result when the input is at V 0.1μF). The first conversion following power-up will be REF or higher (VREFOUT = 1.25V). In an underrange condition (for all input voltages invalid since the reference voltage has not completely below zero scale) the converter will generate the output settled. The first conversion following power up can be code 0. In an overrange condition (for all input voltages discarded using the data abort command or simply read greater than V and ignored. Depending on the value chosen for C REF) the converter will generate the output COMP code 65535. and CREFOUT, the reference startup can take more than one conversion period, see Figure 3. If the startup time is
Input Voltage Range (LTC2472)
less than 1.2ms (833sps output rate) or 4.8ms (208sps output rate) then conversions following the first period As detailed in the Output Data Format section, the output + – are accurate to the device specifications. If the startup code is given as 32768 • (VIN – VIN )/VREF + 32768. For + – time exceeds 1.2ms or 4.8ms then the user can wait the (VIN – VIN ) ≥ VREF, the output code is clamped at 65535 + – appropriate time or use the fixed conversion period as (all ones). For (VIN – VIN ) ≤ –VREF, the output code is a startup timer by ignoring results within the unsettled clamped at 0 (all zeroes). period. Once the reference has settled, all subsequent
Output Data Format
conversion results are valid. If the user places the device The LTC2470/LTC2472 generates a 16-bit direct binary into the sleep mode (SLP = 1, reference powered down) encoded result. It is provided as a 16-bit serial stream the reference will require a startup time proportional to through the SDO output pin under the control of the SCK the value of CCOMP and CREFOUT (see Figure 3). input pin (see Figure 5).
Ease of Use
The LTC2472 (differential input) output code is given by 32768 • (V + – V –)/V The LTC2470/LTC2472 data output has no latency, filter IN IN REF + 32768. The first bit output by the LTC2472, D15, is the MSB, which is 1 for V + ≥ settling delay, or redundant results associated with the IN V – and 0 for V + < V –. This bit is followed by succes- conversion cycle. There is a one-to-one correspondence IN IN IN sively less significant bits (D14, D13, …) until the LSB is between the conversion and the output data. Therefore, output by the LTC2472, see Table 1. multiplexing multiple analog input voltages requires no special actions. The LTC2470 (single-ended input) output code is a direct binary encoded result, see Table 1. The LTC2470/LTC2472 include a proprietary input sampling scheme that reduces the average input current by several During the data output operation the CS input pin must orders of magnitude when compared to traditional delta- be pulled low (CS = LOW). The data output process starts sigma architectures. This allows external filter networks with the most significant bit of the result being present at to interface directly to the LTC2470/LTC2472. Since the the SDO output pin (SDO = D15) once CS goes low. A new average input sampling current is 50nA, an external RC data bit appears at the SDO output pin after each falling lowpass filter using 1kΩ and 0.1µF results in <1LSB edge detected at the SCK input pin. The output data can additional error. Additionally, there is negligible leakage be reliably latched on the rising edge of SCK. current between IN+ and IN– (for the LTC2472). 24702fb For more information www.linear.com/LTC2470 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs Power Requirements Digital Inputs and Digital Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts