Datasheet LTC2439-1 (Analog Devices) - 6

LTC2439-1
PIN FUNCTIONS CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8):
is in a high impedance state. During the Conversion and Analog Inputs. May be programmed for single-ended or Sleep periods, this pin is used as the conversion status differential mode. output. The conversion status can be observed by pulling
V
CS LOW.
CC (Pin 9):
Positive Supply Voltage. Bypass to GND (Pin 15) with a 10µF tantalum capacitor in parallel with
SCK (Pin 18):
Bidirectional Digital Clock Pin. In Internal 0.1µF ceramic capacitor as close to the part as possible. Serial Clock Operation mode, SCK is used as the digital
COM (Pin 10):
The common negative input (IN–) for all output for the internal serial interface clock during the single-ended multiplexer configurations. The voltage on Data Output period. In External Serial Clock Operation Channel 0 to 15 and COM input pins can have any value mode, SCK is used as the digital input for the external se- between GND – 0.3V and V rial interface clock during the Data Output period. A weak CC + 0.3V. Within these limits, the two selected inputs (IN+ and IN–) provide a bipolar internal pull-up is automatically activated in Internal Serial input range (V Clock Operation mode. The Serial Clock Operation mode IN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF. Outside this input range, the converter produces unique is determined by the logic level applied to the SCK pin at overrange and underrange output codes. power up or during the most recent falling edge of CS.
REF+ (Pin 11), REF– (Pin 12):
Differential Reference Input.
FO (Pin 19):
Frequency Control Pin. Digital input that The voltage on these pins can have any value between controls the ADC’s notch frequencies and conversion GND and V time. When the FO pin is connected to GND (FO = 0V), the CC as long as the positive reference input, REF+, is maintained more positive than the negative reference converter uses its internal oscillator and rejects 50Hz and input, REF–, by at least 0.1V. 60Hz simultaneously. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses
GND (Pin 15):
Ground. Connect this pin to a ground plane this signal as its system clock and the digital filter has through a low impedance connection. 87dB minimum rejection in the range fEOSC/2560 ±14%
CS (Pin 16):
Active LOW Digital Input. A LOW on this pin and 110dB minimum rejection at fEOSC/2560 ±4%. enables the SDO digital output and wakes up the ADC.
SDI (Pin 20):
Serial Digital Data Input. During the Data Following each conversion the ADC automatically enters Output period, this pin is used to shift in the multiplexer the Sleep mode and remains in this low power state as address started from the first rising SCK edge. During the long as CS is HIGH. A LOW-to-HIGH transition on CS Conversion and Sleep periods, this pin is in the DON’T during the Data Output transfer aborts the data transfer CARE state. However, a HIGH or LOW logic level should and starts a new conversion. be maintained on SDI in the DON’T CARE mode to avoid
SDO (Pin 17):
Three-State Digital Output. During the Data an excessive current in the SDI input buffers. Output period, this pin is used as the serial data output.
NC (Pins 13, 14):
Not Internally Connected. Do not con- When the chip select CS is HIGH (CS = VCC), the SDO pin nect or connect to ground. 24391fb 6 For more information www.linear.com/LTC2439-1 Document Outline Features Applications Typical Application Absolute Maximum Ratings Order Information Electrical Characteristics Converter Characteristics Analog Input and Reference Digital Inputs and Digital Outputs POWER REQUIREMENTS Timing Characteristics Pin Functions FUNCTIONAL Block Diagram Test CircuitS Applications Information Package Description Revision History Typical Application Related Parts